clkfp.tan.rpt

FPGA中嵌中高级课件,非常有用的课件

; N/A   ; 289.44 MHz ( period = 3.455 ns )               ; state[5]   ; state[5]   ; clk        ; clk      ; None                        ; None                      ; 3.012 ns                ;
; N/A   ; 298.24 MHz ( period = 3.353 ns )               ; state[0]   ; state[14]  ; clk        ; clk      ; None                        ; None                      ; 2.910 ns                ;
; N/A   ; Restricted to 304.04 MHz ( period = 3.289 ns ) ; state[13]  ; state[3]   ; clk        ; clk      ; None                        ; None                      ; 2.844 ns                ;
; N/A   ; Restricted to 304.04 MHz ( period = 3.289 ns ) ; state[13]  ; state[4]   ; clk        ; clk      ; None                        ; None                      ; 2.842 ns                ;
; N/A   ; Restricted to 304.04 MHz ( period = 3.289 ns ) ; state[1]   ; state[14]  ; clk        ; clk      ; None                        ; None                      ; 2.823 ns                ;
; N/A   ; Restricted to 304.04 MHz ( period = 3.289 ns ) ; state[0]   ; state[15]  ; clk        ; clk      ; None                        ; None                      ; 2.822 ns                ;
; N/A   ; Restricted to 304.04 MHz ( period = 3.289 ns ) ; state[12]  ; state[0]   ; clk        ; clk      ; None                        ; None                      ; 2.790 ns                ;
; N/A   ; Restricted to 304.04 MHz ( period = 3.289 ns ) ; state[8]   ; state[0]   ; clk        ; clk      ; None                        ; None                      ; 2.738 ns                ;
; N/A   ; Restricted to 304.04 MHz ( period = 3.289 ns ) ; state[1]   ; state[15]  ; clk        ; clk      ; None                        ; None                      ; 2.735 ns                ;
; N/A   ; Restricted to 304.04 MHz ( period = 3.289 ns ) ; state[0]   ; state[1]   ; clk        ; clk      ; None                        ; None                      ; 2.486 ns                ;
; N/A   ; Restricted to 304.04 MHz ( period = 3.289 ns ) ; state[12]  ; clock~reg0 ; clk        ; clk      ; None                        ; None                      ; 2.476 ns                ;
; N/A   ; Restricted to 304.04 MHz ( period = 3.289 ns ) ; state[8]   ; clock~reg0 ; clk        ; clk      ; None                        ; None                      ; 2.424 ns                ;
; N/A   ; Restricted to 304.04 MHz ( period = 3.289 ns ) ; state[12]  ; state[3]   ; clk        ; clk      ; None                        ; None                      ; 2.280 ns                ;
; N/A   ; Restricted to 304.04 MHz ( period = 3.289 ns ) ; state[12]  ; state[4]   ; clk        ; clk      ; None                        ; None                      ; 2.278 ns                ;
; N/A   ; Restricted to 304.04 MHz ( period = 3.289 ns ) ; state[8]   ; state[3]   ; clk        ; clk      ; None                        ; None                      ; 2.228 ns                ;
; N/A   ; Restricted to 304.04 MHz ( period = 3.289 ns ) ; state[8]   ; state[4]   ; clk        ; clk      ; None                        ; None                      ; 2.226 ns                ;
; N/A   ; Restricted to 304.04 MHz ( period = 3.289 ns ) ; state[14]  ; state[15]  ; clk        ; clk      ; None                        ; None                      ; 2.094 ns                ;
; N/A   ; Restricted to 304.04 MHz ( period = 3.289 ns ) ; state[1]   ; state[1]   ; clk        ; clk      ; None                        ; None                      ; 1.962 ns                ;
; N/A   ; Restricted to 304.04 MHz ( period = 3.289 ns ) ; state[14]  ; state[14]  ; clk        ; clk      ; None                        ; None                      ; 1.668 ns                ;
; N/A   ; Restricted to 304.04 MHz ( period = 3.289 ns ) ; state[15]  ; state[15]  ; clk        ; clk      ; None                        ; None                      ; 1.244 ns                ;
+-------+------------------------------------------------+------------+------------+------------+----------+-----------------------------+---------------------------+-------------------------+


+---------------------------------------------------------------------+
; tco                                                                 ;
+-------+--------------+------------+------------+-------+------------+
; Slack ; Required tco ; Actual tco ; From       ; To    ; From Clock ;
+-------+--------------+------------+------------+-------+------------+
; N/A   ; None         ; 5.680 ns   ; clock~reg0 ; clock ; clk        ;
+-------+--------------+------------+------------+-------+------------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
    Info: Version 7.2 Build 151 09/26/2007 SJ Web Edition
    Info: Processing started: Wed Sep 24 22:27:31 2008
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off clkfp -c clkfp
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Info: Clock "clk" has Internal fmax of 176.52 MHz between source register "state[4]" and destination register "state[0]" (period= 5.665 ns)
    Info: + Longest register to register delay is 5.222 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X5_Y5_N6; Fanout = 4; REG Node = 'state[4]'
        Info: 2: + IC(1.275 ns) + CELL(0.462 ns) = 1.737 ns; Loc. = LC_X5_Y5_N2; Fanout = 1; COMB Node = 'Equal0~147'
        Info: 3: + IC(1.403 ns) + CELL(0.571 ns) = 3.711 ns; Loc. = LC_X5_Y5_N5; Fanout = 4; COMB Node = 'Equal0~150'
        Info: 4: + IC(1.142 ns) + CELL(0.369 ns) = 5.222 ns; Loc. = LC_X5_Y6_N1; Fanout = 4; REG Node = 'state[0]'
        Info: Total cell delay = 1.402 ns ( 26.85 % )
        Info: Total interconnect delay = 3.820 ns ( 73.15 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "clk" to destination register is 2.388 ns
            Info: 1: + IC(0.000 ns) + CELL(0.727 ns) = 0.727 ns; Loc. = PIN_H5; Fanout = 17; CLK Node = 'clk'
            Info: 2: + IC(1.087 ns) + CELL(0.574 ns) = 2.388 ns; Loc. = LC_X5_Y6_N1; Fanout = 4; REG Node = 'state[0]'
            Info: Total cell delay = 1.301 ns ( 54.48 % )
            Info: Total interconnect delay = 1.087 ns ( 45.52 % )
        Info: - Longest clock path from clock "clk" to source register is 2.388 ns
            Info: 1: + IC(0.000 ns) + CELL(0.727 ns) = 0.727 ns; Loc. = PIN_H5; Fanout = 17; CLK Node = 'clk'
            Info: 2: + IC(1.087 ns) + CELL(0.574 ns) = 2.388 ns; Loc. = LC_X5_Y5_N6; Fanout = 4; REG Node = 'state[4]'
            Info: Total cell delay = 1.301 ns ( 54.48 % )
            Info: Total interconnect delay = 1.087 ns ( 45.52 % )
    Info: + Micro clock to output delay of source is 0.235 ns
    Info: + Micro setup delay of destination is 0.208 ns
Info: tco from clock "clk" to destination pin "clock" through register "clock~reg0" is 5.680 ns
    Info: + Longest clock path from clock "clk" to source register is 2.388 ns
        Info: 1: + IC(0.000 ns) + CELL(0.727 ns) = 0.727 ns; Loc. = PIN_H5; Fanout = 17; CLK Node = 'clk'
        Info: 2: + IC(1.087 ns) + CELL(0.574 ns) = 2.388 ns; Loc. = LC_X5_Y5_N9; Fanout = 2; REG Node = 'clock~reg0'
        Info: Total cell delay = 1.301 ns ( 54.48 % )
        Info: Total interconnect delay = 1.087 ns ( 45.52 % )
    Info: + Micro clock to output delay of source is 0.235 ns
    Info: + Longest register to pin delay is 3.057 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X5_Y5_N9; Fanout = 2; REG Node = 'clock~reg0'
        Info: 2: + IC(1.603 ns) + CELL(1.454 ns) = 3.057 ns; Loc. = PIN_K3; Fanout = 0; PIN Node = 'clock'
        Info: Total cell delay = 1.454 ns ( 47.56 % )
        Info: Total interconnect delay = 1.603 ns ( 52.44 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning
    Info: Allocated 112 megabytes of memory during processing
    Info: Processing ended: Wed Sep 24 22:27:36 2008
    Info: Elapsed time: 00:00:05