comp.v

FPGA中嵌中高级课件,非常有用的课件

`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:    11:14:35 05/23/07
// Design Name:    
// Module Name:    comp
// Project Name:   
// Target Device:  
// Tool versions:  
// Description:
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////
module comp(clk,adds,sadd,b1,cosin,coss);
input clk,adds;
input [15:0] sadd;
input [15:0] b1;
output [15:0] cosin;
output coss;
reg [15:0] cosin="0000000000000000";
reg coss="0";
always @(posedge clk) 
begin
 if(adds==1'b1)
 begin
  if(b1>sadd) begin
  cosin<=sadd;
  coss<=1'b1;
  end
  else begin
  cosin<=sadd-16'hc910;
  coss<=1'b1;
  end	
 end 
 else begin
 coss<=1'b0;
 end
end 
endmodule