send2.v

来自「FPGA中嵌中高级课件,非常有用的课件」· Verilog 代码 · 共 72 行

`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:    20:46:08 05/21/07
// Design Name:    
// Module Name:    send2
// Project Name:   
// Target Device:  
// Tool versions:  
// Description:
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////
module send2(clk,ino,coss,cosin,adds,sadd,b1);
input clk,ino,coss;
input[15:0] cosin;
output [15:0] sadd;
output adds;
output [15:0] b1;
reg [15:0] b1="0000000000000000";

reg [15:0] sadd="0000000000000000";
reg adds="0";
reg [7:0] temp="00000000";
always @(posedge clk)
begin
if(coss==1)
sadd<=cosin;
else begin

if(temp==0)
begin
  if(ino==1)
  begin
  sadd<=sadd+16'h00ff;
  temp<=temp+1 ;
  b1<=16'h6488;
  adds<=1'b1;
  end
  else
  begin
  sadd<=sadd+16'h0000;
  b1<=16'h6488;
  temp<=temp+1 ;
  adds<=1'b1;
  end
end
else
begin
  if(temp==8'd1) begin
  adds<=1'b0;
  temp<=temp+1;
  end
  else begin
     if(temp<8'd48)begin
     temp<=temp+1;
     adds<=1'b0;
	  end
     else	temp<=0;
   end
end
end
end

endmodule