📄 cs8950hw.h
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/*
* OpReg_IndAd 0x0050 6-RW Individual Address, IA
*/
/* this place left intentionally blank */
/*
* OpReg_FERMask 0x0064 4-RW Cardbus Function Event Mask Register
*/
#define GIntMask_Interrupt (1L<<0x0F) /* */
/*
* OpReg_TxCollCnt 0x0070 2-RO Transmit Collision Count
*/
/* this place left intentionally blank */
/*
* OpReg_RxMissCnt 0x0074 2-RO Receive Miss Count
*/
/* this place left intentionally blank */
/*
* OpReg_RxRuntCnt 0x0078 2-RO Receive Runt Count
*/
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/*
* OpReg_BMCTL 0x0080 2-RW Bus Master Control
*/
#define BMCTL_ManualTrans (1<<0x0d) /* */
#define BMCTL_TimedTrans (1<<0x0c) /* */
#define BMCTL_UnderrunHalt (1<<0x0b) /* */
#define BMCTL_TxChRes (1<<0x0a) /* */
#define BMCTL_TxDis (1<<0x09) /* */
#define BMCTL_TxEn (1<<0x08) /* */
#define BMCTL_EnHeader2 (1<<0x06) /* */
#define BMCTL_EnHeader1 (1<<0x05) /* */
#define BMCTL_EnEOB (1<<0x04) /* */
#define BMCTL_RxChRes (1<<0x02) /* */
#define BMCTL_RxDis (1<<0x01) /* */
#define BMCTL_RxEn (1<<0x00) /* */
/*
* OpReg_BMSts 0x0084 1-RO Bus Master Status
*/
#define BMSts_TxAct (1<<0x07) /* */
#define BMSts_TransPending (1<<0x04) /* */
#define BMSts_RxAct (1<<0x03) /* */
#define BMSts_QueueID_Mask (0x07) /* */
#define BMSts_QueueID_RxData (0x00) /* */
#define BMSts_QueueID_TxData (0x01) /* */
#define BMSts_QueueID_RxSts (0x02) /* */
#define BMSts_QueueID_TxSts (0x03) /* */
#define BMSts_QueueID_RxDesc (0x04) /* */
#define BMSts_QueueID_TxDesc (0x05) /* */
/*
* OpReg_RxBCA 0x0088 4-RO Receive buffer current address
*/
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/*
* OpReg_TxBCA 0x008C 4-RO Transmit buffer current address
*/
/* this place left intentionally blank */
/*
* OpReg_RxDBA 0x0090 4-RW Receive Descriptor Queue Base Address
*/
/* this place left intentionally blank */
/*
* OpReg_RxDBL 0x0094 2-RW Receive Descriptor Queue Base Length
*/
/* this place left intentionally blank */
/*
* OpReg_RxDCL 0x0096 2-RW Receive Descriptor Queue Current Length
*/
/* this place left intentionally blank */
/*
* OpReg_RxDCA 0x0098 4-RW Receive Descriptor Current Address
*/
/* this place left intentionally blank */
/*
* OpReg_RxDEQ 0x009C 4-RW Receive Descriptor Enqueue
*/
#define RxDEQ_Inc_Mask (0x000000FF) /* */
#define RxDEQ_Value_Mask (0xFFFF0000) /* for reading */
/*
* OpReg_RxSBA 0x00A0 4-RW Receive Status Queue Base Address
*/
/* this place left intentionally blank */
/*
* OpReg_RxSBL 0x00A4 2-RW Receive Status Queue Base Length
*/
/* this place left intentionally blank */
/*
* OpReg_RxSCL 0x00A6 2-RW Receive Status Queue Current Length
*/
/* this place left intentionally blank */
/*
* OpReg_RxSCA 0x00A8 4-RW Receive Status Current Address
*/
/* this place left intentionally blank */
/*
* OpReg_RxSEQ 0x00AC 4-RW Receive Status Enqueue
*/
#define RxSEQ_Inc_Mask (0x000000FF) /* */
#define RxSEQ_Value_Mask (0xFFFF0000) /* for reading */
/*
* OpReg_TxDBA 0x00B0 4-RW Transmit Descriptor Queue Base Address
*/
/* this place left intentionally blank */
/*
* OpReg_TxDBL 0x00B4 2-RW Transmit Descriptor Queue Base Length
*/
/* this place left intentionally blank */
/*
* OpReg_TxDCL 0x00B6 2-RW Transmit Descriptor Queue Current Length
*/
/* this place left intentionally blank */
/*
* OpReg_TxDCA 0x00B8 4-RW Transmit Descriptor Current Address
*/
/* this place left intentionally blank */
/*
* OpReg_TxDEQ 0x00BC 4-RW Transmit Descriptor Enqueue
*/
#define TxDEQ_Inc_Mask (0x000000FF) /* */
#define TxDEQ_Value_Mask (0xFFFF0000) /* for reading */
/*
* OpReg_TxSBA 0x00C0 4-RW Transmit status Queue Base Address
*/
/* this place left intentionally blank */
/*
* OpReg_TxSBL 0x00C4 2-RW Transmit Status Queue Base Length
*/
/* this place left intentionally blank */
/*
* OpReg_TxSCL 0x00C6 2-RW Transmit Status Queue Current Length
*/
/* this place left intentionally blank */
/*
* OpReg_TxSCA 0x00C8 4-RW Transmit Status Current Address
*/
/* this place left intentionally blank */
/*
* OpReg_RxBTH 0x00D0 4-RW Receive Buffer Threshold
*/
#define RxBTH_SoftTh_Mask (0x000003FF) /* */
#define RxBTH_HardTh_Mask (0x03FF0000) /* */
/*
* OpReg_TxBTH 0x00D4 4-RW Transmit Buffer Threshold
*/
#define TxBTH_SoftTh_Mask (0x000003FF) /* */
#define TxBTH_HardTh_Mask (0x03FF0000) /* */
/*
* OpReg_RxSTH 0x00D8 4-RW Receive Status Threshold
*/
#define RxSTH_SoftTh_Mask (0x0000003F) /* */
#define RxSTH_HardTh_Mask (0x003F0000) /* */
/*
* OpReg_TxSTH 0x00DC 4-RW Transmit Status Threshold
*/
#define TxSTH_SoftTh_Mask (0x0000003F) /* */
#define TxSTH_HardTh_Mask (0x003F0000) /* */
/*
* OpReg_RxDTH 0x00E0 4-RW Receive Descriptor Threshold
*/
#define RxDTH_SoftTh_Mask (0x0000003F) /* */
#define RxDTH_HardTh_Mask (0x003F0000) /* */
/*
* OpReg_TxDTH 0x00E4 4-RW Transmit Descriptor Threshold
*/
#define TxDTH_SoftTh_Mask (0x0000003F) /* */
#define TxDTH_HardTh_Mask (0x003F0000) /* */
/*
* OpReg_MaxFL 0x00E8 4-RW Maximum Frame Length
*/
#define MaxFL_TxStartTh_Mask (0x000007FF) /* */
#define MaxFL_FrameLen_Mask (0x07FF0000) /* */
/*
* OpReg_RxHLen 0x00EC 4-RW Receive Header Length
*/
#define RxHLen_1_Mask (0x000007FF) /* */
#define RxHLen_2_Mask (0x07FF0000) /* */
#endif // _CS8950HW_H_
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