📄 cs8950hw.h
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/************************************************************************
* BEGIN_MANUAL_ENTRY
* Filename: cs8950hw.h
*
* Modification History:
*
* 5/30/2000 Melody Lee
* Created the file
*
* END_MANUAL_ENTRY
*************************************************************************/
#ifndef _CS8950HW_H_
#define _CS8950HW_H_
#define ReadByte( bOffset ) (*(volatile PBYTE const)(gdwEthernetBase + bOffset))
//#define ReadByte( bOffset ) (((volatile PBYTE)gdwEthernetBase)[(volatile unsigned long)bOffset])
//#define ReadByte( bOffset ) (*(volatile PBYTE volatile )(gdwEthernetBase + bOffset))
//#define ReadByte( bOffset ) ((BYTE)(*(volatile PDWORD const)(gdwEthernetBase + bOffset)))
#define WriteByte( bOffset, Value ) (*(volatile PBYTE const)(gdwEthernetBase + bOffset) = Value)
#define ReadWord( wOffset ) (*(volatile PWORD const)(gdwEthernetBase + wOffset))
#define WriteWord( wOffset, Value ) (*(volatile PWORD const)(gdwEthernetBase + wOffset) = Value)
#define ReadDWord( dwOffset ) (*(volatile PDWORD const)(gdwEthernetBase + dwOffset))
#define WriteDWord( dwOffset, Value ) (*(volatile PDWORD const)(gdwEthernetBase + dwOffset) = Value)
/*
* 15.2 PCI Operational Registers
* (The addresses shown are relative to the IO base address register)
*/
#define OpReg_RxCTL 0x0000 /* 4-RW Receive Control */
#define OpReg_TxCTL 0x0004 /* 1-RW Transmit Control */
#define OpReg_TestCTL 0x0008 /* 1-RW Test Control */
#define OpReg_MIICmd 0x0010 /* 2-RW MII(Media Independent Intf) Command */
#define OpReg_MIIData 0x0014 /* 2-RW MII Data */
#define OpReg_MIISts 0x0018 /* 1-RO MII Status */
#define OpReg_SelfCTL 0x0020 /* 1-RW Self Control for LED interface */
#define OpReg_IntEn 0x0024 /* 4-RW Interrupt Enable */
#define OpReg_IntStsP 0x0028 /* 4-RW Interrupt Status Preserve */
#define OpReg_IntStsC 0x002C /* 4-RO Interrupt Status Clear */
#define OpReg_GT 0x0040 /* 4-RW General Timer */
#define OpReg_FCT 0x0044 /* 4-RO Flow Control Timer */
#define OpReg_FCF 0x0048 /* 4-RW Flow Control Format */
#define OpReg_AFP 0x004C /* 1-RW Address Filter Pointer */
#define OpReg_HashTb 0x0050 /* 8-RW Logical Address Filter (Hash Table) */
#define OpReg_IndAd 0x0050 /* 6-RW Individual Address, IA */
#define OpReg_FERMask 0x0064 /* 4-RW Cardbus Function Event Mask Register */
#define OpReg_TxCollCnt 0x0070 /* 2-RO Transmit Collision Count */
#define OpReg_RxMissCnt 0x0074 /* 2-RO Receive Miss Count */
#define OpReg_RxRuntCnt 0x0078 /* 2-RO Receive Runt Count */
#define OpReg_BMCTL 0x0080 /* 2-RW Bus Master Control */
#define OpReg_BMSts 0x0084 /* 1-RO Bus Master Status */
#define OpReg_RxBCA 0x0088 /* 4-RO Receive buffer current address, a.k.a. RBCA */
#define OpReg_TxBCA 0x008C /* 4-RO Transmit buffer current address, a.k.a. TBCA */
#define OpReg_RxDBA 0x0090 /* 4-RW Receive Descriptor Queue Base Address */
#define OpReg_RxDBL 0x0094 /* 2-RW Receive Descriptor Queue Base Length */
#define OpReg_RxDCL 0x0096 /* 2-RW Receive Descriptor Queue Current Length */
#define OpReg_RxDCA 0x0098 /* 4-RW Receive Descriptor Current Address */
#define OpReg_RxDEQ 0x009C /* 4-RW Receive Descriptor Enqueue */
#define OpReg_RxSBA 0x00A0 /* 4-RW Receive Status Queue Base Address */
#define OpReg_RxSBL 0x00A4 /* 2-RW Receive Status Queue Base Length */
#define OpReg_RxSCL 0x00A6 /* 2-RW Receive Status Queue Current Length */
#define OpReg_RxSCA 0x00A8 /* 4-RW Receive Status Current Address */
#define OpReg_RxSEQ 0x00AC /* 4-RW Receive Status Enqueue */
#define OpReg_TxDBA 0x00B0 /* 4-RW Transmit Descriptor Queue Base Address */
#define OpReg_TxDBL 0x00B4 /* 2-RW Transmit Descriptor Queue Base Length */
#define OpReg_TxDCL 0x00B6 /* 2-RW Transmit Descriptor Queue Current Length */
#define OpReg_TxDCA 0x00B8 /* 4-RW Transmit Descriptor Current Address */
#define OpReg_TxDEQ 0x00BC /* 4-RW Transmit Descriptor Enqueue */
#define OpReg_TxSBA 0x00C0 /* 4-RW Transmit status Queue Base Address */
#define OpReg_TxSBL 0x00C4 /* 2-RW Transmit Status Queue Base Length */
#define OpReg_TxSCL 0x00C6 /* 2-RW Transmit Status Queue Current Length */
#define OpReg_TxSCA 0x00C8 /* 4-RW Transmit Status Current Address */
#define OpReg_RxBTH 0x00D0 /* 4-RW Receive Buffer Threshold */
#define OpReg_TxBTH 0x00D4 /* 4-RW Transmit Buffer Threshold */
#define OpReg_RxSTH 0x00D8 /* 4-RW Receive Status Threshold */
#define OpReg_TxSTH 0x00DC /* 4-RW Transmit Status Threshold */
#define OpReg_RxDTH 0x00E0 /* 4-RW Receive Descriptor Threshold */
#define OpReg_TxDTH 0x00E4 /* 4-RW Transmit Descriptor Threshold */
#define OpReg_MaxFL 0x00E8 /* 4-RW Maximum Frame Length */
#define OpReg_RxHLen 0x00EC /* 4-RW Receive Header Length */
#define OpReg_MacCfg0 0x0100 /* 4-RW MAC Configuration Register 0 */
#define OpReg_MacCfg1 0x0104 /* 4-RW MAC Configuration Register 1 */
#define OpReg_MacCfg2 0x0108 /* 4-RW MAC Configuration Register 2 */
#define OpReg_MacCfg3 0x010C /* 4-RW MAC Configuration Register 3 */
#define MAC_FIFO_RAM (OpReg_BASE + 0x1000)
/***************************************************************************/
/***************************************************************************/
/*
* OpReg_RxCTL 0x0000 4-RW Receive Control
*/
#define RxCTL_PauseAccept (1L<<0x14) /* */
#define RxCTL_RxFlowControlEn1 (1L<<0x13) /* */
#define RxCTL_RxFlowControlEn0 (1L<<0x12) /* */
#define RxCTL_BufferCRC (1L<<0x11) /* */
#define RxCTL_SerRxON (1L<<0x10) /* */
#define RxCTL_RuntCRCA (1L<<0x0D) /* */
#define RxCTL_RuntA (1L<<0x0C) /* */
#define RxCTL_PromiscuousA (1L<<0x0B) /* */
#define RxCTL_BroadcastA (1L<<0x0A) /* */
#define RxCTL_MulticastA (1L<<0x09) /* */
#define RxCTL_IAHashA (1L<<0x08) /* */
#define RxCTL_IndividualAccept3 (1L<<0x03) /* */
#define RxCTL_IndividualAccept2 (1L<<0x02) /* */
#define RxCTL_IndividualAccept1 (1L<<0x01) /* */
#define RxCTL_IndividualAccept0 (1L<<0x00) /* */
/*
* OpReg_TxCTL 0x0004 1-RW Transmit Control
*/
#define TxCTL_2PartDefDis (1<<0x07) /* */
#define TxCTL_ModBackOffE (1<<0x06) /* */
#define TxCTL_InhibitCRC (1<<0x05) /* */
#define TxCTL_TxPadDis (1<<0x04) /* */
#define TxCTL_OneColl (1<<0x03) /* */
#define TxCTL_SendPause (1<<0x02) /* */
#define TxCTL_PauseBusy (1<<0x01) /* */
#define TxCTL_SerTxON (1<<0x00) /* */
/*
* OpReg_TestCTL 0x0008 1-RW Test Control
*/
#define TestCTL_MACFast (1<<0x07) /* */
#define TestCTL_MACFDX (1<<0x06) /* */
#define TestCTL_DisableBackoff (1<<0x05) /* */
#define TestCTL_MIIFast (1<<0x04) /* */
/*
* OpReg_MIICmd 0x0010 2-RW MII(Media Independent Intf) Command
*/
#define MIICmd_RegAd_Mask (0x001F) /* */
#define MIICmd_PhyAd_Mask (0x03E0) /* */
#define MIICmd_Opcode_Mask (0xC000) /* */
/** QQQQQQQ */
#define MIICmd_PhyAd_8950 (0x0000) /* Address the 8950 Phy */
#define MIICmd_Opcode_Read (0x8000) /* Read register */
#define MIICmd_Opcode_Write (0x4000) /* Write register */
/*
* OpReg_MIIData 0x0014 2-RW MII Data
*/
/* this place left intentionally blank */
/*
* OpReg_MIISts 0x0018 1-RO MII Status
*/
#define MIISts_Busy (1<<0x00) /* */
/*
* OpReg_SelfCTL 0x0020 1-RW Self Control for LED interface
*/
#define SelfCTL_MDCDIV_Mask (0x7E00)
#define SelfCTL_MDCDIV_Shift 9
#define SelfCTL_PSPRS (1<<0x08) /* */
#define SelfCTL_WakeupViaLAN (1<<0x07) /* */
#define SelfCTL_GPO (1<<0x05) /* */
#define SelfCTL_PoweredUpWakeupEn (1<<0x04) /* */
#define SelfCTL_PoweredDownWakeupEn (1<<0x03) /* */
#define SelfCTL_MIILoopback (1<<0x02) /* */
#define SelfCTL_RESET (1<<0x00) /* */
/*
* OpReg_IntEn 0x0024 4-RW Interrupt Enable
*/
#define IntEn_WakeupViaLANiE (1L<<0x1e) /* */
#define IntEn_RxMissiE (1L<<0x1d) /* */
#define IntEn_RxBuffersiE (1L<<0x1c) /* */
#define IntEn_RxStsQiE (1L<<0x1b) /* */
#define IntEn_TxLenErriE (1L<<0x1a) /* */
#define IntEn_EndofChainiE (1L<<0x19) /* */
#define IntEn_TxUnderrunHaltiE (1L<<0x18) /* */
#define IntEn_MissOviE (1L<<0x12) /* */
#define IntEn_TxCollOviE (1L<<0x11) /* */
#define IntEn_RxRuntOviE (1L<<0x10) /* */
#define IntEn_MIIStsiE (1L<<0x0c) /* */
#define IntEn_PhyStsiE (1L<<0x0b) /* */
#define IntEn_TimeoutiE (1L<<0x0a) /* */
#define IntEn_SWintiE (1L<<0x08) /* */
#define IntEn_TxStsQiE (1L<<0x03) /* */
#define IntEn_RxEOFiE (1L<<0x02) /* */
#define IntEn_RxEOBiE (1L<<0x01) /* */
#define IntEn_RxHdriE (1L<<0x00) /* */
/*
* OpReg_IntStsP 0x0028 4-RW Interrupt Status Preserve
* OpReg_IntStsC 0x002C 4-RO Interrupt Status Clear
*/
#define IntSts_WakeupViaLAN (1L<<0x1e) /* */
#define IntSts_RxMiss (1L<<0x1d) /* */
#define IntSts_RxBuffers (1L<<0x1c) /* */
#define IntSts_RxStsSEQ (1L<<0x1b) /* */
#define IntSts_TxLenErr (1L<<0x1a) /* */
#define IntSts_EndofChain (1L<<0x19) /* */
#define IntSts_TxUnderrunHalt (1L<<0x18) /* */
#define IntSts_MissOv (1L<<0x12) /* */
#define IntSts_TxCollOv (1L<<0x11) /* */
#define IntSts_RxRuntOv (1L<<0x10) /* */
#define IntSts_MIISts (1L<<0x0c) /* */
#define IntSts_PhySts (1L<<0x0b) /* */
#define IntSts_Timeout (1L<<0x0a) /* */
#define IntSts_SWint (1L<<0x08) /* */
#define IntSts_Other (1L<<0x04) /* */
#define IntSts_TxStsQ (1L<<0x03) /* */
#define IntSts_RxStsQ (1L<<0x02) /* */
/*
* OpReg_GT 0x0040 4-RW General Timer
*/
#define GT_Count_Mask (0xFFFF0000) /* */
#define GT_Period_Mask (0x0000FFFF) /* */
/*
* OpReg_FCT 0x0044 4-RO Flow Control Timer
*/
#define FCT_Timer_Mask (0x00FFFFFF) /* */
/*
* OpReg_FCF 0x0048 4-RW Flow Control Format
*/
#define FCF_MACCTLType_Mask (0xFFFF0000) /* */
#define FCF_TxPauseTime_Mask (0x0000FFFF) /* */
/*
* OpReg_AFP 0x004C 1-RW Address Filter Pointer
*/
#define AFP_Mask (0x07) /* */
#define AFP_IAPrimary (0x00) /* primary IA for Wakeup, Tx pause and Rx pause frames */
#define AFP_IASecondary1 (0x01) /* secondary IA for Rx pause frames */
#define AFP_IASecondary2 (0x02) /* secondary IA for qualifying Rx frames */
#define AFP_IASecondary3 (0x03) /* secondary IA for qualifying Rx frames */
#define AFP_Tx (0x06) /* destination address for Tx */
#define AFP_Hash (0x07) /* hash table */
/*
* OpReg_HashTb 0x0050 8-RW Logical Address Filter (Hash Table)
*/
/* this place left intentionally blank */
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