cs8950.c

wince.net板级支持包BSP for EP9315

        }
        else if ( ((PHYID.DWord & PHYID_OUI_Mask)   == PHYID_OUI_Crystal) &&
                ((PHYID.DWord & PHYID_Model_Mask) == PHYID_Model_CS8952) )
        {
            pCD->PHYType = PHY_TYPE_CRYSTAL;
            EdbgOutputDebugString("Detected Crystal PHY at address: %x\r\n", PHYAddress);
         break;
        }
        else if ( ((PHYID.DWord & PHYID_OUI_Mask)   == PHYID_OUI_ICS) &&
                ((PHYID.DWord & PHYID_Model_Mask) == PHYID_Model_ICS1890) )
        {
            pCD->PHYType = PHY_TYPE_ICS;
            break;
        }
        else if ( ((PHYID.DWord & PHYID_OUI_Mask)   == PHYID_OUI_BROADCOM) &&
                ((PHYID.DWord & PHYID_Model_Mask) == PHYID_Model_BCM5201) )
        {                                                                  
            pCD->PHYType = PHY_TYPE_BROADCOM;                              
            EdbgOutputDebugString("Detected Broadcom PHY at address: %x\r\n", PHYAddress);
         break;                                                            
        }                                                                  

        // !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
        // 
        // !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
        else if (PHYID.DWord == 0x00406212)
        {
            pCD->PHYType = PHY_TYPE_BROADCOM;
            EdbgOutputDebugString("Detected Broadcom PHY at address: %x\r\n", PHYAddress);
            break;
        }
        else if (PHYID.DWord == 0x78100003)
        {
            pCD->PHYType = PHY_TYPE_LEVEL1; /* clc */
            EdbgOutputDebugString("Detected Level1 PHY at address: %x\r\n", PHYAddress);
            break;
        }
    }

    /* If did not find a known PHY */
    if ( PHYAddress == 32 )
    {
        EdbgOutputDebugString("A known PHY is not found!\r\n");
        return FALSE;
    }

    /* Save the address of the PHY */
    pCD->PHYAddress = PHYAddress;

    /* Get the PHY revision level */
    pCD->PHYRevision = (BYTE)(PHYID.DWord & PHYID_Revision_Mask);

    return TRUE;
}




/******************************************************************************
*
* StartupQueues()
*
******************************************************************************/
static WORD StartupQueues( PCHIP pChip )
{
    PCD     pCD;
    USHORT   Index;

    pCD    = (PCD)pChip->pData;

    pCD->TxQueueDepth=0;
    
    /* Allocate shared memory for the Receive Descriptor Queue */
    pCD->pRxDesc        = (PVOID) &pCS8950Buffer->RxDesc[0];
    pCD->RxDescPhysAddr = CONVERT_TO_PHYSICAL(pCD->pRxDesc);
    ASSERT(!(pCD->RxDescPhysAddr & 0x3));

    /* Initialize Receive Descriptor Queue limit pointer */
    pCD->pRxDescLimit = pCD->pRxDesc + RXDESCCOUNT;

    /* Initialize the Receive Descriptor Queue registers */
    WriteDWord( OpReg_RxDBA, pCD->RxDescPhysAddr );
    WriteWord(  OpReg_RxDBL, sizeof(RxDesc_t)*RXDESCCOUNT );
    WriteDWord( OpReg_RxDTH, 0x00040002);

    /* Allocate shared memory for the Receive Status Queue */
    pCD->pRxStat        = (PVOID) &pCS8950Buffer->RxStat[0];
    pCD->RxStatPhysAddr = CONVERT_TO_PHYSICAL(pCD->pRxStat);
    ASSERT(!(pCD->RxStatPhysAddr & 0x3));

    /* Initialize Receive Status Queue limit pointer */
    pCD->pRxStatLimit = pCD->pRxStat + RXSTATCOUNT;

    /* Initialize the Receive Status Queue registers */
    WriteDWord( OpReg_RxSBA, pCD->RxStatPhysAddr );
    WriteWord( OpReg_RxSBL, sizeof(RxStat_t)*RXSTATCOUNT);
    WriteDWord(OpReg_RxSTH, 0x00040002);

    /* Allocate shared memory for the Transmit Descriptor Queue */
    pCD->pTxDesc        = (PVOID) &pCS8950Buffer->TxDesc[0];
    pCD->TxDescPhysAddr = CONVERT_TO_PHYSICAL(pCD->pTxDesc);
    ASSERT(!(pCD->TxDescPhysAddr & 0x3));
    //Result = VosAllocSharedMemory( pChip, (WORD)(sizeof(TxDesc_t)*TXDESCCOUNT),
    //     (PVOID *)(&pCD->pTxDesc), (DWORD *)(&pCD->TxDescPhysAddr) );
    //     
    //if ( Result != TRUE ) 
    //    return FALSE;

    /* Initialize Transmit Descriptor Queue limit pointer */
    pCD->pTxDescLimit = pCD->pTxDesc + TXDESCCOUNT;

    /* Initialize the Transmit Descriptor Queue registers */
    WriteDWord( OpReg_TxDBA, pCD->TxDescPhysAddr );
    WriteWord( OpReg_TxDBL, sizeof(TxDesc_t)*TXDESCCOUNT );
    WriteDWord( OpReg_TxDTH, 0x00040002);

    /* Allocate shared memory for the Transmit Status Queue */
    pCD->pTxStat        = (PVOID) &pCS8950Buffer->TxStat[0];
    pCD->TxStatPhysAddr = CONVERT_TO_PHYSICAL(pCD->pTxStat);
    ASSERT(!(pCD->TxStatPhysAddr & 0x3));
    //Result = VosAllocSharedMemory( pChip, (WORD)(sizeof(TxStat_t)*TXSTATCOUNT),
    //     (PVOID *)(&pCD->pTxStat), (DWORD *)(&pCD->TxStatPhysAddr) );
    //     
    //if ( Result != TRUE ) 
    //    return FALSE;

    /* Initialize Transmit Status Queue limit pointer */
    pCD->pTxStatLimit = pCD->pTxStat + TXSTATCOUNT;

    /* Initialize the Transmit Status Queue registers */
    WriteDWord( OpReg_TxSBA, pCD->TxStatPhysAddr );
    WriteWord(  OpReg_TxSBL, sizeof(TxStat_t)*TXSTATCOUNT );
    WriteDWord( OpReg_TxSTH, 0x00040002 );

    /* Allocate receive buffers and initialize the Receive Descriptor Queue */
    for ( Index=0; Index<RXDESCCOUNT; Index++ )
    {
        /* Allocate shared memory for a receive buffer */
        pCD->RxBuff[Index].pBuff    = (PVOID) &pCS8950Buffer->RxBuff[Index][0];
        pCD->RxBuff[Index].PhysAddr = CONVERT_TO_PHYSICAL( pCD->RxBuff[Index].pBuff);
        ASSERT(!(pCD->RxBuff[0].PhysAddr & 0x3));
    
        /* Initialize the Receive Descriptor */
        pCD->pRxDesc[Index].RxBufAdr  = pCD->RxBuff[Index].PhysAddr;
        pCD->pRxDesc[Index].BufLength = RXBUFFSIZE;
        pCD->pRxDesc[Index].BufIndx   = Index;
    }        

    //    /* Allocate shared memory for a receive buffer */
    //    Result = VosAllocSharedMemory( pChip, (WORD)RXBUFFSIZE,
    //        (PVOID *)(&pCD->RxBuff[Index].pBuff), (DWORD *)(&pCD->RxBuff[Index].PhysAddr));
    //    if ( Result != TRUE ) return FALSE;
    //
    //    /* Initialize the Receive Descriptor */
    //    (pCD->pRxDesc+Index)->RxBufAdr  = pCD->RxBuff[Index].PhysAddr;
    //    (pCD->pRxDesc+Index)->BufLength = RXBUFFSIZE;
    //    (pCD->pRxDesc+Index)->BufIndx   = Index;
    //}
    
    //
    //

    /* Allocate the transmit buffers */
    //for ( Index=0; Index<TXBUFFCOUNT; Index++ )
    //{
    //    /* Allocate shared memory for a transmit buffer */
    //    Result = VosAllocSharedMemory( pChip, (WORD)TXBUFFSIZE,
    //        (PVOID *)(&pCD->TxBuff[Index].pBuff), (DWORD *)(&pCD->TxBuff[Index].PhysAddr) );
    //    if ( Result != TRUE ) 
    //    {
    //        return FALSE;
    //    }                
    //}
    for ( Index=0; Index<TXBUFFCOUNT; Index++ )
    {
        /* Allocate the transmit buffers */
        pCD->TxBuff[Index].pBuff    = (PVOID) &pCS8950Buffer->TxBuff[Index][0];
        pCD->TxBuff[Index].PhysAddr = CONVERT_TO_PHYSICAL( pCD->TxBuff[Index].pBuff);
        #if 0
        EdbgOutputDebugString("psEP9312Buffer                          = %x\n", pCS8950Buffer);
        EdbgOutputDebugString("psEP9312Buffer->TxBuff                  = %x\n", pCS8950Buffer->TxBuff);
        EdbgOutputDebugString("psEP9312Buffer->TxBuff[Index]           = %x\n", pCS8950Buffer->TxBuff[Index]);
        EdbgOutputDebugString("psEP9312Buffer->TxBuff[Index][0]        = %x\n", pCS8950Buffer->TxBuff[Index][0]);
        EdbgOutputDebugString("pCD->TxBuff[Index].PhysAddr              = %x\n", pCD->TxBuff[Index].PhysAddr);
        #endif // 0
        ASSERT(pCD->TxBuff[Index].pBuff);
        ASSERT(pCD->TxBuff[Index].PhysAddr);
        ASSERT(!(pCD->TxBuff[Index].PhysAddr & 0x3));
    }        


    /* Initialize receive and transmit buffer thresholds */
    WriteDWord( OpReg_RxBTH, 0x00800040 );
    WriteDWord( OpReg_TxBTH, 0x00200010 );

    //
    // Need to make sure that we don't need this.
    //
    //InitializeRxQueues( pChip );


    return MAC_SUCCESSFUL;
}





/******************************************************************************
*
* VchipInit()
*
******************************************************************************/

static WORD VchipInit( PCHIP pChip )
{
    PCD             pCD;
    int             x;
    // WORD            Result;
    volatile BYTE   Status;


    pCD    = (PCD)pChip->pData;
 

    /* Reset the queues */
    ResetQueues( pChip );


    /* Enable the transmit descriptor processor */
    WriteWord( OpReg_BMCTL,  BMCTL_TxEn );

    /* Wait until the transmit descriptor processor is active */
    for ( x=0; x<MAXLOOP; x++ )
    {
        DelayInuSec(1);
        Status=ReadByte( OpReg_BMSts);
        if ( Status & BMSts_TxAct ) 
            break;
    }
    if ( x == MAXLOOP )
    {
        EdbgOutputDebugString("the transmit descriptor processor is not active!\n");
        return MAC_FAILED;
    }


    /* Enable the receive descriptor processor */  
    WriteWord( OpReg_BMCTL,  BMCTL_RxEn );

    /* Wait until the receive descriptor processor is active */
    for ( x=0; x<MAXLOOP; x++ )
    {
        DelayInuSec(1);
        Status=ReadByte( OpReg_BMSts);
        if ( Status & BMSts_RxAct ) break;
    }
    if ( x == MAXLOOP )
    {
        EdbgOutputDebugString("the receive descriptor processor is not active!\r\n");
        return MAC_FAILED;
    }


    /* Enqueue all the Receive Descriptors to the chip */
    WriteDWord(OpReg_RxDEQ, RXDESCCOUNT );

    /* Enqueue all the Receive Status entries to the chip */
    WriteDWord( OpReg_RxSEQ, RXSTATCOUNT );

   /* Use MII registers to reset or initialize the PHY chip? */

   // Put some text in here why 10/Full is necessary for external
   // loopback mode.
   /* If full duplex mode was negotiated by the PHY then set   */
   /* the MAC FDX bit in the TestCtl register (10 Mbps only?). */
   // WriteByte( OpReg_TestCTL, TestCTL_MACFast | TestCTL_MACFDX);
 /*   if ( Global_test_type == 0 ) //Loopback 
    {
      WriteByte( OpReg_TestCTL,  TestCTL_MACFDX);
    }
*/
   /* Initialize the Transmit Control register */
/*  WriteByte( OpReg_TxCTL, TxCTL_SerTxON | TxCTL_InhibitCRC);*/
    WriteByte( OpReg_TxCTL, TxCTL_SerTxON );

    /* Initialize the Receive Control register */
    //********************************************************************
    // From EP9312 errata
    //
    // Description: 
    //      The ethernet Mac does not correctly receive frames that have a 
    //      size of 64 bytes.
    //
    // Workaround:
    //      In order to receive frames of 64 bytes, enable the RCRCA bit in
    //      the RxCTRL register.  This will allow the ethernet controller
    //      to ingore the CRC information and not discard the frames.
    //
    // The Windows CE ethernet debugger sends lots of frames that are
    // 64 bytes in length.
    //********************************************************************
    WriteDWord( OpReg_RxCTL, RxCTL_SerRxON | RxCTL_RuntCRCA );

    /* Initialize the filtering criteria */ 
    VchipChangeFiltering(FILTER_INDIVIDUAL_ACCEPT | FILTER_BROADCAST_ACCEPT);
    /*  WriteByte(OpReg_SelfCTL, ReadByte( OpReg_SelfCTL)| SelfCTL_MIILoopback);*/

    return MAC_SUCCESSFUL;
}


/******************************************************************************
*
* VchipReset()
*
******************************************************************************/

static WORD VchipReset( PCHIP pChip )
{
    volatile BYTE Status;
    int  x;


    /* Reset the chip */
    WriteByte( OpReg_SelfCTL, SelfCTL_RESET );

    /* Wait until the reset is complete */
    for ( x=0; x<MAXLOOP; x++ )
    {
        Status=ReadByte( OpReg_SelfCTL);
        if ( !(Status & SelfCTL_RESET) ) 
            break;
    }
    if ( x == MAXLOOP )
    {
        EdbgOutputDebugString("The CS Chip reset does not complete!\r\n");
        return MAC_FAILED;
    }
    
    return MAC_SUCCESSFUL;
}

/******************************************************************************
*
* ResetQueues()
*
******************************************************************************/
static void ResetQueues( PCHIP pChip )
{
    PCD   pCD;
    RxDesc_t *pRxDesc;
    RxStat_t *pRxStat;
    TxStat_t *pTxStat;

    pCD    = (PCD)pChip->pData;

    /* Set receive descriptor queue current address to the base address */
    WriteDWord( OpReg_RxDCA, pCD->RxDescPhysAddr );

    /* Set receive status queue current address to the base address */
    WriteDWord( OpReg_RxSCA, pCD->RxStatPhysAddr );

    /* Set transmit descriptor queue current address to the base address */
    WriteDWord( OpReg_TxDCA, pCD->TxDescPhysAddr );

    /* Set transmit status queue current address to the base address */
    WriteDWord( OpReg_TxSCA, pCD->TxStatPhysAddr );

    /* Set the queue pointers to be beginning of the queues */
    pCD->pRxStatNext = pCD->pRxStat;
    pCD->pTxStatNext = pCD->pTxStat;
    pCD->pTxDescNext = pCD->pTxDesc;


    /* No Tx frames that have been euqueued but Tx status haven't been processed yet. */
    pCD->TxQueueDepth=0;


    /* No frames have been transmitted (without underruns) yet */
    pCD->TxGoodCount = 0;

    /* Start filling in the transmit request table at index zero */
    pCD->TxReqIndex = 0;

    /* All the transmit descriptors are available */
    pCD->TxDescAvail = TXDESCCOUNT;

    /* Set all the receive descriptors to available (not held) */
    for ( pRxDesc=pCD->pRxDesc; pRxDesc<pCD->pRxDescLimit; pRxDesc++ )
      pRxDesc->BufLength = RXBUFFSIZE;

    /* Clear all the Frame Processed flags in the receive status queue */
    for ( pRxStat=pCD->pRxStat; pRxStat<pCD->pRxStatLimit; pRxStat++ )
        pRxStat->RxStat = 0;

    /* Clear all the Frame Processed flags in the transmit status queue */
    for ( pTxStat=pCD->pTxStat; pTxStat<pCD->pTxStatLimit; pTxStat++ )
        pTxStat->TxStat = 0;
}

/******************************************************************************
*
* VchipChangeFiltering()
*
******************************************************************************/
void VchipChangeFiltering(unsigned int uiFilteringOpts)
{
    DWORD RxControl;


    /* Get the current settings of the receiver control register */
    RxControl=ReadDWord( OpReg_RxCTL);

    /* Turn off the receiver while changing the filtering criteria */
    WriteDWord( OpReg_RxCTL, RxControl & ~RxCTL_SerRxON );

    /* Clear all of the accept bits */
    RxControl &= ~(RxCTL_IndividualAccept0 | RxCTL_BroadcastA |
         RxCTL_MulticastA | RxCTL_PromiscuousA);

    /* Set only the specified accept bits */
    if (uiFilteringOpts & FILTER_INDIVIDUAL_ACCEPT )
        RxControl |= RxCTL_IndividualAccept0;
    if (uiFilteringOpts & FILTER_BROADCAST_ACCEPT )
        RxControl |= RxCTL_BroadcastA;
    if (uiFilteringOpts & FILTER_MULTICAST_ACCEPT )
        RxControl |= RxCTL_MulticastA;
    if (uiFilteringOpts & FILTER_PROMISCUOUS_ACCEPT )
        RxControl |= RxCTL_PromiscuousA;

    /* Write the new filtering criteria to the chip and turn receiver back on */
    WriteDWord( OpReg_RxCTL, RxControl );
}




/******************************************************************************
*
* VpsRecvError(()
*
******************************************************************************/
static void VpsRecvError( PCHIP pChip, WORD Errors )
{
   Global_RxNotOkCnt++;

    // Keep track of OKs, Errors and confirm packet if necessary
    //if (Errors & RX_ERR_CRC_ERROR){
    //  EdbgOutputDebugString("VpsRecvError(): RX_ERR_CRC_ERROR\n");
    //}
    if (Errors & RX_ERR_EXTRA_DATA)
    {
        EdbgOutputDebugString("VpsRecvError(): RX_ERR_EXTRA_DATA\n");
    }

    if (Errors & RX_ERR_RUNT)
    {
        EdbgOutputDebugString("VpsRecvError(): RX_ERR_RUNT\n");
    }
    if (Errors & RX_ERR_FRAMING)
    {
        EdbgOutputDebugString("VpsRecvError(): RX_ERR_FRAMING\n");
    }
    if (Errors & RX_ERR_OVERRUN)
    {
        EdbgOutputDebugString("VpsRecvError(): RX_ERR_OVERRUN\n");
    }
    if (Errors & RX_ERR_RX_ERR)
    {
        EdbgOutputDebugString("VpsRecvError(): RX_ERR_RX_ERR\n");
    }
    if (Errors & RX_ERR_RX_MISS)
    {
        EdbgOutputDebugString("VpsRecvError(): RX_ERR_RX_MISS\n");
    }
    if (Errors & RX_ERR_DRIBBLE)
    {
        EdbgOutputDebugString("VpsRecvError(): RX_ERR_DRIBBLE\n");
    }
    if (Errors & RX_ERR_TOO_MANY_FRAGS)
    {
        EdbgOutputDebugString("VpsRecvError(): RX_ERR_TOO_MANY_FRAGS\n");
    }