📄 promise_ide.c
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status = pciConfigOutByte(
BusNo, /* bus number */
DeviceNo, /* device number */
FuncNo, /* function number */
drive_pci|0x02,/* offset into the configuration space */
CP|0x02 /* data write from offset */
);
speed = ATA_DMA_ULTRA_W_1;
} else if ((id->ultraDma & 0x0001) && (udma_33)) {
if (!((id->ultraDma >> 8) & 1)) {
id->ultraDma &= ~0x0F00;
id->ultraDma |= 0x0101;
id->multiDma &= ~0x0F00;
id->singleDma &= ~0x0F00;
}
/* speed 4 == UDMA mode 0 */
status = pciConfigOutByte(
BusNo, /* bus number */
DeviceNo, /* device number */
FuncNo, /* function number */
drive_pci|0x01,/* offset into the configuration space */
BP|0x60 /* data write from offset */
);
status = pciConfigOutByte(
BusNo, /* bus number */
DeviceNo, /* device number */
FuncNo, /* function number */
drive_pci|0x02,/* offset into the configuration space */
CP|0x03 /* data write from offset */
);
speed = ATA_DMA_ULTRA_W_0;
} else if (id->multiDma & 0x0004) {
if (!((id->multiDma >> 8) & 4)) {
id->multiDma &= ~0x0F00;
id->multiDma |= 0x0404;
id->singleDma &= ~0x0F00;
}
/* speed 4 == DMA mode 2 multi-word */
status = pciConfigOutByte(
BusNo, /* bus number */
DeviceNo, /* device number */
FuncNo, /* function number */
drive_pci|0x01,/* offset into the configuration space */
BP|0x60 /* data write from offset */
);
status = pciConfigOutByte(
BusNo, /* bus number */
DeviceNo, /* device number */
FuncNo, /* function number */
drive_pci|0x02,/* offset into the configuration space */
CP|0x03 /* data write from offset */
);
speed = ATA_DMA_MULTI_W_2;
} else if (id->multiDma & 0x0002) {
if (!((id->multiDma >> 8) & 2)) {
id->multiDma &= ~0x0F00;
id->multiDma |= 0x0202;
id->singleDma &= ~0x0F00;
}
/* speed 3 == DMA mode 1 multi-word */
status = pciConfigOutByte(
BusNo, /* bus number */
DeviceNo, /* device number */
FuncNo, /* function number */
drive_pci|0x01,/* offset into the configuration space */
BP|0x60 /* data write from offset */
);
status = pciConfigOutByte(
BusNo, /* bus number */
DeviceNo, /* device number */
FuncNo, /* function number */
drive_pci|0x02,/* offset into the configuration space */
CP|0x04 /* data write from offset */
);
speed = ATA_DMA_MULTI_W_1;
} else if (id->multiDma & 0x0001) {
if (!((id->multiDma >> 8) & 1)) {
id->multiDma &= ~0x0F00;
id->multiDma |= 0x0101;
id->singleDma &= ~0x0F00;
}
/* speed 2 == DMA mode 0 multi-word */
status = pciConfigOutByte(
BusNo, /* bus number */
DeviceNo, /* device number */
FuncNo, /* function number */
drive_pci|0x01,/* offset into the configuration space */
BP|0x60 /* data write from offset */
);
status = pciConfigOutByte(
BusNo, /* bus number */
DeviceNo, /* device number */
FuncNo, /* function number */
drive_pci|0x02,/* offset into the configuration space */
CP|0x05 /* data write from offset */
);
speed = ATA_DMA_MULTI_W_0;
} else if (id->singleDma & 0x0004) {
if (!((id->singleDma >> 8) & 4)) {
id->multiDma &= ~0x0F00;
id->singleDma &= ~0x0F00;
id->singleDma |= 0x0404;
}
/* speed 2 == DMA mode 2 single-word */
status = pciConfigOutByte(
BusNo, /* bus number */
DeviceNo, /* device number */
FuncNo, /* function number */
drive_pci|0x01,/* offset into the configuration space */
BP|0x60 /* data write from offset */
);
status = pciConfigOutByte(
BusNo, /* bus number */
DeviceNo, /* device number */
FuncNo, /* function number */
drive_pci|0x02,/* offset into the configuration space */
CP|0x05 /* data write from offset */
);
speed = ATA_DMA_SINGLE_W_2;
} else if (id->singleDma & 0x0002) {
if (!((id->singleDma >> 8) & 2)) {
id->multiDma &= ~0x0F00;
id->singleDma &= ~0x0F00;
id->singleDma |= 0x0202;
}
/* speed 1 == DMA mode 1 single-word */
status = pciConfigOutByte(
BusNo, /* bus number */
DeviceNo, /* device number */
FuncNo, /* function number */
drive_pci|0x01,/* offset into the configuration space */
BP|0x80 /* data write from offset */
);
status = pciConfigOutByte(
BusNo, /* bus number */
DeviceNo, /* device number */
FuncNo, /* function number */
drive_pci|0x02,/* offset into the configuration space */
CP|0x06 /* data write from offset */
);
speed = ATA_DMA_SINGLE_W_1;
} else if (id->singleDma & 0x0001) {
if (!((id->singleDma >> 8) & 1)) {
id->multiDma &= ~0x0F00;
id->singleDma &= ~0x0F00;
id->singleDma |= 0x0101;
}
/* speed 0 == DMA mode 0 single-word */
status = pciConfigOutByte(
BusNo, /* bus number */
DeviceNo, /* device number */
FuncNo, /* function number */
drive_pci|0x01,/* offset into the configuration space */
BP|0xc0 /* data write from offset */
);
status = pciConfigOutByte(
BusNo, /* bus number */
DeviceNo, /* device number */
FuncNo, /* function number */
drive_pci|0x02,/* offset into the configuration space */
CP|0x0B /* data write from offset */
);
speed = ATA_DMA_SINGLE_W_0;
} else {
/* restore original pci-config space */
status = pciConfigOutLong(
BusNo, /* bus number */
DeviceNo, /* device number */
FuncNo, /* function number */
drive_pci, /* offset into the configuration space */
drive_conf /* data write from offset */
);
return ide_dma_off_quietly;
}
#if PDC202XX_DECODE_REGISTER_INFO
status = pciConfigInByte(
BusNo, /* bus number */
DeviceNo, /* device number */
FuncNo, /* function number */
drive_pci, /* offset into the configuration space */
&AP /* data write from offset */
);
status = pciConfigInByte(
BusNo, /* bus number */
DeviceNo, /* device number */
FuncNo, /* function number */
drive_pci|0x01,/* offset into the configuration space */
&BP /* data write from offset */
);
status = pciConfigInByte(
BusNo, /* bus number */
DeviceNo, /* device number */
FuncNo, /* function number */
drive_pci|0x02,/* offset into the configuration space */
&CP /* data write from offset */
);
decode_registers(REG_A, AP);
decode_registers(REG_B, BP);
decode_registers(REG_C, CP);
decode_registers(REG_D, DP);
taskDelay(10);
#endif /* PDC202XX_DECODE_REGISTER_INFO */
/* Set the control register to use the 66Mhz system
clock for UDMA 3/4 mode operation. If one drive on
a channel is U66 capable but the other isn't we
fall back to U33 mode. The BIOS INT 13 hooks turn
the clock on then off for each read/write issued. I don't
do that here because it would require modifying the
kernel, seperating the fop routines from the kernel or
somehow hooking the fops calls. It may also be possible to
leave the 66Mhz clock on and readjust the timing
parameters. */
#if 1
base_add4 = baseAddress[4];
CLKSPD = sysInByte(base_add4+0x11);
status = pciConfigInWord(
BusNo, /* bus number */
DeviceNo, /* device number */
FuncNo, /* function number */
0x50, /* offset into the configuration space */
&CIS /* data write from offset */
);
ultra_66 = 0;
/* check again for when we use BIOS timing */
if ((id->ultraDma & 0x0010) || (id->ultraDma & 0x0008)) {
ultra_66 = 1;
}
ultra_66 = (udma) ? ultra_66 : 0;
if (!ctrl) {/* primary channel */
if ((ultra_66) && ( CIS & (1<<10) )) {
printf("ULTRA66: Warning: Primary channel of Ultra 66 requires an 80-pin cable for Ultra66 operation.\nSwitching to Ultra33 mode.\n");
/* zero second bit */
sysOutByte( (baseAddress[4] + (drive*8))+0x11,CLKSPD & ~0x02);
} else {
if (ultra_66) {
/* check to make sure drive on same channel is u66 capable */
if (pCtrl->drives == 2) {
if ((pCtrl->drive[!drive].param.ultraDma & 0x0010) ||
(pCtrl->drive[!drive].param.ultraDma & 0x0008)) {
sysOutByte(base_add4+0x11,CLKSPD | 0x02);
} else {
sysOutByte((baseAddress[4] + (drive*8))+0x11,CLKSPD & ~0x02);
}
} else {/* udma4 drive by itself */
sysOutByte(base_add4+0x11,CLKSPD | 0x02);
}
} else {
sysOutByte((baseAddress[4] + (drive*8))+0x11,CLKSPD & ~0x02);
}
}
} else {/* secondary channel */
if ((ultra_66) && ( CIS & (1<<11) )) {
printf("ULTRA66: Warning: Secondary channel of Ultra 66 requires an 80-pin cable for Ultra66 operation.\nSwitching to Ultra33 mode.\n");
/* zero out fourth bit */
sysOutByte(base_add4+0x11,CLKSPD & ~0x08);
} else {
if (ultra_66) {
/* check to make sure drive on same channel is u66 capable */
if (pCtrl->drives==2) {
if ((pCtrl->drive[!drive].param.ultraDma & 0x0010) ||
(pCtrl->drive[!drive].param.ultraDma & 0x0008)) {
sysOutByte(base_add4+0x11,CLKSPD | 0x08);
} else{
sysOutByte(base_add4+0x11,CLKSPD & ~0x08);
}
} else {/* udma4 drive by itself */
sysOutByte(base_add4+0x11,CLKSPD | 0x08);
}
} else {
sysOutByte(base_add4+0x11,CLKSPD & ~0x08);
}
}
}
#endif
#if PROMISE_DEBUG
ataPrintSpeed(speed);
taskDelay(10);
#endif
(void) ataCmd(
ctrl,
drive,
ATA_CMD_SET_FEATURE,
ATA_SUB_SET_RWMODE,
speed
);
if (ctrl == 0)
ataDmaConfig(ctrl,baseAddress[4]);
else
ataDmaConfig(ctrl,baseAddress[4] + 8);
return ((int)((id->ultraDma >> 11) & 3) ? ide_dma_on :
((id->ultraDma >> 8) & 7) ? ide_dma_on :
((id->multiDma >> 8) & 7) ? ide_dma_on :
((id->singleDma >> 8) & 7) ? ide_dma_on :
ide_dma_off_quietly);
}
#endif //config for dma
/////////////////////////////////debug///////////////////////////////////////////
// ctrl - which IDE controller to mount
//
extern void startup_hard_drive(int ctrl)
{ /* initialize hard disk driver */
IMPORT ATA_RESOURCE ataResources[];
ATA_RESOURCE *pAtaResource;
if (ctrl > 1) {
printf("syntax: startup_hard_drive 0 - start ATA controller 0\n");
printf(" startup_hard_drive 1 - start ATA controller 1\n");
return;
}
ataInitPromise();
taskDelay(10);
pAtaResource = &ataResources[ctrl];
if (pAtaResource->ctrlType == IDE_LOCAL)
ataDrv (ctrl, pAtaResource->drives, pAtaResource->intVector,
pAtaResource->intLevel, pAtaResource->configType,
pAtaResource->semTimeout, pAtaResource->wdgTimeout);
}
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