top.twr

来自FPGA开发板的PS2开发源代码

--------------------------------------------------------------------------------
Release 7.1i Trace H.38
Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.

C:/Xilinx/bin/nt/trce.exe -ise
d:\parttime\for book\}
Design file:              top.ncd
Physical constraint file: top.pcf
Device,speed:             xc3s400,-4 (PRODUCTION 1.35 2005-01-22)
Report level:             error report

Environment Variable      Effect 
--------------------      ------ 
NONE                      No environment variables were set
--------------------------------------------------------------------------------

INFO:Timing:2698 - No timing constraints found, doing default enumeration.
INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths
   option. All paths that are not constrained will be reported in the
   unconstrained paths section(s) of the report.


Data Sheet report:
-----------------
All values displayed in nanoseconds (ns)

Setup/Hold to clock clk
------------+------------+------------+------------------+--------+
            |  Setup to  |  Hold to   |                  |  Clock |
Source      | clk (edge) | clk (edge) |Internal Clock(s) |  Phase |
------------+------------+------------+------------------+--------+
rst         |    4.208(R)|   -1.861(R)|clk_BUFGP         |   0.000|
------------+------------+------------+------------------+--------+

Clock to Setup on destination clock clk
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
clk            |    4.836|         |         |         |
---------------+---------+---------+---------+---------+

Analysis completed Thu May 29 23:59:00 2008
--------------------------------------------------------------------------------



Peak Memory Usage: 88 MB