top_synthesis.nlf

来自FPGA开发板的PS2开发源代码

Release 7.1i - netgen H.38
Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.

Command Line: netgen -intstyle ise -w -ofmt verilog -sim top.ngc
top_synthesis.v  

Reading design 'top.ngc' ...
Flattening design ...
Processing design ... 
  Preping design's networks ...
  Preping design's macros ...
Writing Verilog netlist file 'top_synthesis.v' ...
INFO:NetListWriters:633 - The generated Verilog netlist contains Xilinx UNISIM
   simulation primitives and has to be used with UNISIM simulation library for
   correct compilation and simulation. 
Number of warnings: 0
Number of info messages: 1
Total memory usage is 44912 kilobytes