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来自FPGA开发板的PS2开发源代码

-------------------------------------------------------------------------
Delay:               4.274ns (Levels of Logic = 7)
  Source:            XLXI_1/count_1 (FF)
  Destination:       XLXI_1/count_6 (FF)
  Source Clock:      clk rising
  Destination Clock: clk rising

  Data Path: XLXI_1/count_1 to XLXI_1/count_6
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC:C->Q              1   0.720   1.140  XLXI_1/count_1 (XLXI_1/count_1)
     LUT1:I0->O            1   0.551   0.000  XLXI_1/count_1_rt (XLXI_1/count_1_rt)
     MUXCY:S->O            1   0.500   0.000  top_XLXI_1/_old_count_7<1>cy (top_XLXI_1/_old_count_7<1>_cyo)
     MUXCY:CI->O           1   0.064   0.000  top_XLXI_1/_old_count_7<2>cy (top_XLXI_1/_old_count_7<2>_cyo)
     MUXCY:CI->O           1   0.064   0.000  top_XLXI_1/_old_count_7<3>cy (top_XLXI_1/_old_count_7<3>_cyo)
     MUXCY:CI->O           1   0.064   0.000  top_XLXI_1/_old_count_7<4>cy (top_XLXI_1/_old_count_7<4>_cyo)
     MUXCY:CI->O           0   0.064   0.000  top_XLXI_1/_old_count_7<5>cy (top_XLXI_1/_old_count_7<5>_cyo)
     XORCY:CI->O           2   0.904   0.000  top_XLXI_1/_old_count_7<6>_xor (XLXI_1/_old_count_7<6>)
     FDC:D                     0.203          XLXI_1/count_6
    ----------------------------------------
    Total                      4.274ns (3.134ns logic, 1.140ns route)
                                       (73.3% logic, 26.7% route)

=========================================================================
Timing constraint: Default period analysis for Clock 'XLXI_1/clk:Q'
  Clock period: 7.705ns (frequency: 129.786MHz)
  Total number of paths / destination ports: 1627 / 188
-------------------------------------------------------------------------
Delay:               7.705ns (Levels of Logic = 5)
  Source:            XLXI_4/timer_5usec_count_1 (FF)
  Destination:       XLXI_4/m1_state_0 (FF)
  Source Clock:      XLXI_1/clk:Q rising
  Destination Clock: XLXI_1/clk:Q rising

  Data Path: XLXI_4/timer_5usec_count_1 to XLXI_4/m1_state_0
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDRE:C->Q             2   0.720   1.216  XLXI_4/timer_5usec_count_1 (XLXI_4/timer_5usec_count_1)
     LUT4_D:I0->O          1   0.551   0.827  XLXI_4/timer_5usec_done18 (CHOICE1948)
     LUT4:I3->O            5   0.551   0.989  XLXI_4/timer_5usec_done21 (XLXI_4/timer_5usec_done)
     LUT4:I2->O            1   0.551   0.827  XLXI_4/m1_next_state<0>109 (CHOICE2335)
     LUT4_L:I3->LO         1   0.551   0.168  XLXI_4/m1_next_state<0>134 (CHOICE2344)
     LUT4_D:I2->LO         1   0.551   0.000  XLXI_4/m1_next_state<0>199 (N2480)
     FDS:D                     0.203          XLXI_4/m1_state_0
    ----------------------------------------
    Total                      7.705ns (3.678ns logic, 4.027ns route)
                                       (47.7% logic, 52.3% route)

=========================================================================
Timing constraint: Default period analysis for Clock 'XLXI_3/clk_int:Q'
  Clock period: 7.618ns (frequency: 131.268MHz)
  Total number of paths / destination ports: 569 / 32
-------------------------------------------------------------------------
Delay:               7.618ns (Levels of Logic = 4)
  Source:            XLXI_3/count_2 (FF)
  Destination:       XLXI_3/data_4 (FF)
  Source Clock:      XLXI_3/clk_int:Q rising
  Destination Clock: XLXI_3/clk_int:Q rising

  Data Path: XLXI_3/count_2 to XLXI_3/data_4
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDE:C->Q              5   0.720   1.260  XLXI_3/count_2 (XLXI_3/count_2)
     LUT4_D:I0->O          3   0.551   1.102  XLXI_3/_n0002_SW0 (N1283)
     LUT4:I1->O            1   0.551   1.140  XLXI_3/Ker6_SW0 (N186)
     LUT4_D:I0->O          5   0.551   0.989  XLXI_3/Ker6 (XLXI_3/N6)
     LUT3_L:I2->LO         1   0.551   0.000  XLXI_3/_n002613 (XLXI_3/_n0026)
     FDE:D                     0.203          XLXI_3/data_3
    ----------------------------------------
    Total                      7.618ns (3.127ns logic, 4.491ns route)
                                       (41.0% logic, 59.0% route)

=========================================================================
Timing constraint: Default period analysis for Clock 'XLXI_2/count_3:Q'
  Clock period: 6.889ns (frequency: 145.159MHz)
  Total number of paths / destination ports: 392 / 32
-------------------------------------------------------------------------
Delay:               6.889ns (Levels of Logic = 3)
  Source:            XLXI_3/clkcnt_4 (FF)
  Destination:       XLXI_3/clkcnt_14 (FF)
  Source Clock:      XLXI_2/count_3:Q rising
  Destination Clock: XLXI_2/count_3:Q rising

  Data Path: XLXI_3/clkcnt_4 to XLXI_3/clkcnt_14
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDR:C->Q              2   0.720   1.216  XLXI_3/clkcnt_4 (XLXI_3/clkcnt_4)
     LUT2:I0->O            1   0.551   0.869  XLXI_3/_n003236 (CHOICE1855)
     LUT4_D:I2->LO         1   0.551   0.168  XLXI_3/_n003258 (N2494)
     LUT4:I2->O           16   0.551   1.237  XLXI_3/_n00161 (XLXI_3/_n0016)
     FDR:R                     1.026          XLXI_3/clkcnt_0
    ----------------------------------------
    Total                      6.889ns (3.399ns logic, 3.490ns route)
                                       (49.3% logic, 50.7% route)

=========================================================================
Timing constraint: Default period analysis for Clock 'XLXI_3/_n003268:O'
  Clock period: 3.182ns (frequency: 314.268MHz)
  Total number of paths / destination ports: 1 / 1
-------------------------------------------------------------------------
Delay:               3.182ns (Levels of Logic = 1)
  Source:            XLXI_3/clkdiv (FF)
  Destination:       XLXI_3/clkdiv (FF)
  Source Clock:      XLXI_3/_n003268:O rising
  Destination Clock: XLXI_3/_n003268:O rising

  Data Path: XLXI_3/clkdiv to XLXI_3/clkdiv
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDR:C->Q              3   0.720   0.907  XLXI_3/clkdiv (XLXI_3/clkdiv)
     INV:I->O              1   0.551   0.801  XLXI_3/_n00411_INV_0 (XLXI_3/_n0041)
     FDR:D                     0.203          XLXI_3/clkdiv
    ----------------------------------------
    Total                      3.182ns (1.474ns logic, 1.708ns route)
                                       (46.3% logic, 53.7% route)

=========================================================================
Timing constraint: Default period analysis for Clock 'XLXI_3/clkdiv:Q'
  Clock period: 5.296ns (frequency: 188.831MHz)
  Total number of paths / destination ports: 2 / 2
-------------------------------------------------------------------------
Delay:               5.296ns (Levels of Logic = 2)
  Source:            XLXI_3/clk_int (FF)
  Destination:       XLXI_3/clk_int (FF)
  Source Clock:      XLXI_3/clkdiv:Q rising
  Destination Clock: XLXI_3/clkdiv:Q rising

  Data Path: XLXI_3/clk_int to XLXI_3/clk_int
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDR:C->Q              1   0.720   0.801  XLXI_3/clk_int (XLXI_3/clk_int1)
     BUFG:I->O            26   0.401   1.819  XLXI_3/clk_int_BUFG (XLXI_3/clk_int)
     INV:I->O              1   0.551   0.801  XLXI_3/_n00421_INV_0 (XLXI_3/_n0042)
     FDR:D                     0.203          XLXI_3/clk_int
    ----------------------------------------
    Total                      5.296ns (1.875ns logic, 3.421ns route)
                                       (35.4% logic, 64.6% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'XLXI_1/clk:Q'
  Total number of paths / destination ports: 70 / 66
-------------------------------------------------------------------------
Offset:              6.122ns (Levels of Logic = 3)
  Source:            rst (PAD)
  Destination:       XLXI_4/bit_count_2 (FF)
  Destination Clock: XLXI_1/clk:Q rising

  Data Path: rst to XLXI_4/bit_count_2
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O             5   0.821   1.260  rst_IBUF (rst_IBUF)
     LUT3:I0->O            1   0.551   0.996  XLXI_4/_n000533_SW1 (N2355)
     LUT4:I1->O            4   0.551   0.917  XLXI_4/_n000544 (XLXI_4/_n0005)
     FDRE:R                    1.026          XLXI_4/bit_count_0
    ----------------------------------------
    Total                      6.122ns (2.949ns logic, 3.173ns route)
                                       (48.2% logic, 51.8% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'clk'
  Total number of paths / destination ports: 1 / 1
-------------------------------------------------------------------------
Offset:              2.344ns (Levels of Logic = 1)
  Source:            rst (PAD)
  Destination:       XLXI_1/clk (FF)
  Destination Clock: clk rising

  Data Path: rst to XLXI_1/clk
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O             5   0.821   0.921  rst_IBUF (rst_IBUF)
     FDE:CE                    0.602          XLXI_1/clk
    ----------------------------------------
    Total                      2.344ns (1.423ns logic, 0.921ns route)
                                       (60.7% logic, 39.3% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'XLXI_1/clk:Q'
  Total number of paths / destination ports: 20 / 9
-------------------------------------------------------------------------
Offset:              10.338ns (Levels of Logic = 3)
  Source:            XLXI_4/m1_state_1 (FF)
  Destination:       ps2dk (PAD)
  Source Clock:      XLXI_1/clk:Q rising

  Data Path: XLXI_4/m1_state_1 to ps2dk
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDRS:C->Q            27   0.720   2.019  XLXI_4/m1_state_1 (XLXI_4/m1_state_1)
     LUT4:I1->O            1   0.551   0.000  XLXI_4/ps2_data_hi_z111_G (N2284)
     MUXF5:I1->O           1   0.360   0.801  XLXI_4/ps2_data_hi_z111 (XLXI_4/ps2_data_hi_z)
     IOBUF:T->IO               5.887          ps2dk_IOBUF (ps2dk)
    ----------------------------------------
    Total                     10.338ns (7.518ns logic, 2.820ns route)
                                       (72.7% logic, 27.3% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'XLXI_3/clkdiv:Q'
  Total number of paths / destination ports: 1 / 1
-------------------------------------------------------------------------
Offset:              7.241ns (Levels of Logic = 1)
  Source:            XLXI_3/lcd_e (FF)
  Destination:       lcd_e (PAD)
  Source Clock:      XLXI_3/clkdiv:Q falling

  Data Path: XLXI_3/lcd_e to lcd_e
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDR_1:C->Q            2   0.720   0.877  XLXI_3/lcd_e (XLXI_3/lcd_e)
     OBUF:I->O                 5.644          lcd_e_OBUF (lcd_e)
    ----------------------------------------
    Total                      7.241ns (6.364ns logic, 0.877ns route)
                                       (87.9% logic, 12.1% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'XLXI_3/clk_int:Q'
  Total number of paths / destination ports: 9 / 9
-------------------------------------------------------------------------
Offset:              7.271ns (Levels of Logic = 1)
  Source:            XLXI_3/data_6 (FF)
  Destination:       data<6> (PAD)
  Source Clock:      XLXI_3/clk_int:Q rising

  Data Path: XLXI_3/data_6 to data<6>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDE:C->Q              3   0.720   0.907  XLXI_3/data_6 (XLXI_3/data_6)
     OBUF:I->O                 5.644          data_6_OBUF (data<6>)
    ----------------------------------------
    Total                      7.271ns (6.364ns logic, 0.907ns route)
                                       (87.5% logic, 12.5% route)

=========================================================================
CPU : 32.84 / 33.45 s | Elapsed : 33.00 / 33.00 s
 
--> 

Total memory usage is 103620 kilobytes

Number of errors   :    0 (   0 filtered)
Number of warnings :   31 (   0 filtered)
Number of infos    :    5 (   0 filtered)