butterfly1.map.qmsg

这是一个蝶行运算单元,是做FFT的最基本的单元

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.0 Build 178 04/27/2006 SJ Full Version " "Info: Version 6.0 Build 178 04/27/2006 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Thu Nov 09 21:30:29 2006 " "Info: Processing started: Thu Nov 09 21:30:29 2006" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off butterfly1 -c butterfly1 " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off butterfly1 -c butterfly1" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "butterfly1.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file butterfly1.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 butterfly1-bhv " "Info: Found design unit 1: butterfly1-bhv" {  } { { "butterfly1.vhd" "" { Text "D:/software/Altera.Quartus.II.v6.0-SHooTERS/win/pan/cpld/butterfly/11-9-1/butterfly1.vhd" 14 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 butterfly1 " "Info: Found entity 1: butterfly1" {  } { { "butterfly1.vhd" "" { Text "D:/software/Altera.Quartus.II.v6.0-SHooTERS/win/pan/cpld/butterfly/11-9-1/butterfly1.vhd" 7 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "butterfly1 " "Info: Elaborating entity \"butterfly1\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Warning" "WSUTIL_SUTIL_QOR_LOSS_DUE_TO_CYCLONE_WYS_TARGETED_FOR_CYCLONE_II" "" "Warning: Resynthesizing Cyclone or Stratix WYSIWYG primitives into Cyclone II WYSIWYG primitives; however, resynthesized WYSIWYG primitives may not produce optimal compilation results." {  } {  } 0 0 "Resynthesizing Cyclone or Stratix WYSIWYG primitives into Cyclone II WYSIWYG primitives; however, resynthesized WYSIWYG primitives may not produce optimal compilation results." 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../../../../../libraries/megafunctions/lpm_mult.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../../../../../libraries/megafunctions/lpm_mult.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_mult " "Info: Found entity 1: lpm_mult" {  } { { "lpm_mult.tdf" "" { Text "d:/software/altera.quartus.ii.v6.0-shooters/libraries/megafunctions/lpm_mult.tdf" 281 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_ELABORATION_HEADER" "lpm_mult:Mult0 " "Info: Elaborated megafunction instantiation \"lpm_mult:Mult0\"" {  } { { "butterfly1.vhd" "" { Text "D:/software/Altera.Quartus.II.v6.0-SHooTERS/win/pan/cpld/butterfly/11-9-1/butterfly1.vhd" 24 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/mult_dr01.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/mult_dr01.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 mult_dr01 " "Info: Found entity 1: mult_dr01" {  } { { "db/mult_dr01.tdf" "" { Text "D:/software/Altera.Quartus.II.v6.0-SHooTERS/win/pan/cpld/butterfly/11-9-1/db/mult_dr01.tdf" 32 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "192 " "Info: Implemented 192 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "40 " "Info: Implemented 40 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "40 " "Info: Implemented 40 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0} { "Info" "ISCL_SCL_TM_LCELLS" "108 " "Info: Implemented 108 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0} { "Info" "ISCL_SCL_TM_DSP_ELEM" "4 " "Info: Implemented 4 DSP elements" {  } {  } 0 0 "Implemented %1!d! DSP elements" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 1  Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Thu Nov 09 21:30:32 2006 " "Info: Processing ended: Thu Nov 09 21:30:32 2006" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Info: Elapsed time: 00:00:03" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}