butterfly1.tan.rpt

这是一个蝶行运算单元,是做FFT的最基本的单元

Timing Analyzer report for butterfly1
Thu Nov 09 21:30:55 2006
Version 6.0 Build 178 04/27/2006 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Timing Analyzer Summary
  3. Timing Analyzer Settings
  4. tpd
  5. Timing Analyzer Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2006 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+----------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary                                                                                                          ;
+------------------------------+-------+---------------+-------------+----------+-----------+------------+----------+--------------+
; Type                         ; Slack ; Required Time ; Actual Time ; From     ; To        ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+-------------+----------+-----------+------------+----------+--------------+
; Worst-case tpd               ; N/A   ; None          ; 21.799 ns   ; in2_i[2] ; out1_r[9] ; --         ; --       ; 0            ;
; Total number of failed paths ;       ;               ;             ;          ;           ;            ;          ; 0            ;
+------------------------------+-------+---------------+-------------+----------+-----------+------------+----------+--------------+


+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                             ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                ; Setting            ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                           ; EP2C20F256C6       ;      ;    ;             ;
; Timing Models                                         ; Final              ;      ;    ;             ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;             ;
; Number of paths to report                             ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                          ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                ; Off                ;      ;    ;             ;
; Report IO Paths Separately                            ; Off                ;      ;    ;             ;
; Default hold multicycle                               ; Same As Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                      ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                 ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements               ; On                 ;      ;    ;             ;
; Enable Recovery/Removal analysis                      ; Off                ;      ;    ;             ;
; Enable Clock Latency                                  ; Off                ;      ;    ;             ;
; Use TimeQuest Timing Analyzer                         ; Off                ;      ;    ;             ;
+-------------------------------------------------------+--------------------+------+----+-------------+


+----------------------------------------------------------------------------------------------------------------------------------------+
; tpd                                                                                                                                    ;
+-----------------------------------------+-----------------------------------------------------+-----------------+----------+-----------+
; Slack                                   ; Required P2P Time                                   ; Actual P2P Time ; From     ; To        ;
+-----------------------------------------+-----------------------------------------------------+-----------------+----------+-----------+
; N/A                                     ; None                                                ; 21.799 ns       ; in2_i[2] ; out1_r[9] ;
; N/A                                     ; None                                                ; 21.772 ns       ; in2_i[3] ; out1_r[9] ;
; N/A                                     ; None                                                ; 21.768 ns       ; in2_i[2] ; out2_r[8] ;
; N/A                                     ; None                                                ; 21.749 ns       ; in2_i[4] ; out1_r[9] ;
; N/A                                     ; None                                                ; 21.741 ns       ; in2_i[3] ; out2_r[8] ;
; N/A                                     ; None                                                ; 21.718 ns       ; in2_i[4] ; out2_r[8] ;
; N/A                                     ; None                                                ; 21.711 ns       ; in2_i[2] ; out2_r[9] ;
; N/A                                     ; None                                                ; 21.684 ns       ; in2_i[3] ; out2_r[9] ;
; N/A                                     ; None                                                ; 21.661 ns       ; in2_i[4] ; out2_r[9] ;
; N/A                                     ; None                                                ; 21.537 ns       ; in2_i[2] ; out1_i[8] ;
; N/A                                     ; None                                                ; 21.515 ns       ; in2_i[2] ; out2_r[6] ;
; N/A                                     ; None                                                ; 21.510 ns       ; in2_i[3] ; out1_i[8] ;
; N/A                                     ; None                                                ; 21.495 ns       ; in2_i[6] ; out1_r[9] ;
; N/A                                     ; None                                                ; 21.488 ns       ; in2_i[3] ; out2_r[6] ;
; N/A                                     ; None                                                ; 21.487 ns       ; in2_i[4] ; out1_i[8] ;
; N/A                                     ; None                                                ; 21.466 ns       ; in2_i[5] ; out1_r[9] ;
; N/A                                     ; None                                                ; 21.465 ns       ; in2_i[4] ; out2_r[6] ;
; N/A                                     ; None                                                ; 21.464 ns       ; in2_i[6] ; out2_r[8] ;
; N/A                                     ; None                                                ; 21.435 ns       ; in2_i[5] ; out2_r[8] ;
; N/A                                     ; None                                                ; 21.407 ns       ; in2_i[6] ; out2_r[9] ;
; N/A                                     ; None                                                ; 21.378 ns       ; in2_i[5] ; out2_r[9] ;
; N/A                                     ; None                                                ; 21.345 ns       ; in2_i[2] ; out1_r[4] ;
; N/A                                     ; None                                                ; 21.318 ns       ; in2_i[3] ; out1_r[4] ;
; N/A                                     ; None                                                ; 21.305 ns       ; in2_i[2] ; out2_r[4] ;
; N/A                                     ; None                                                ; 21.295 ns       ; in2_i[4] ; out1_r[4] ;
; N/A                                     ; None                                                ; 21.278 ns       ; in2_i[3] ; out2_r[4] ;
; N/A                                     ; None                                                ; 21.265 ns       ; in2_i[2] ; out1_r[7] ;
; N/A                                     ; None                                                ; 21.255 ns       ; in2_i[4] ; out2_r[4] ;
; N/A                                     ; None                                                ; 21.238 ns       ; in2_i[3] ; out1_r[7] ;
; N/A                                     ; None                                                ; 21.233 ns       ; in2_i[6] ; out1_i[8] ;