📄 cpldbus51_tb.vhd
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library ieee;
use ieee.STD_LOGIC_UNSIGNED.all;
use ieee.std_logic_1164.all;
entity cpldbus51_tb is
end cpldbus51_tb;
architecture TB_ARCHITECTURE of cpldbus51_tb is
-- Component declaration of the tested unit
component cpldbus51
port(
Clk : in std_logic;
Clr : in std_logic;
P0 : inout std_logic_vector(7 downto 0);
P2 : in std_logic_vector(7 downto 0);
ALE : in std_logic;
Wr : in std_logic;
Rd : in std_logic;
Pina : out std_logic;
nCS8255 : out std_logic;
RamBank : out std_logic_vector(1 downto 0);
nCsFlashRam : out std_logic;
FlashRomBank : out std_logic_vector(2 downto 0) );
end component;
-- Stimulus signals - signals mapped to the input and inout ports of tested entity
signal Clk : std_logic;
signal Clr : std_logic;
signal P0 : std_logic_vector(7 downto 0);
signal P2 : std_logic_vector(7 downto 0);
signal ALE : std_logic;
signal Wr : std_logic;
signal Rd : std_logic;
-- Observed signals - signals mapped to the output ports of tested entity
signal Pina : std_logic;
signal nCS8255 : std_logic;
signal RamBank : std_logic_vector(1 downto 0);
signal nCsFlashRam : std_logic;
signal FlashRomBank : std_logic_vector(2 downto 0);
-- Add your code here ...
constant Systick :time :=62.5ns; --16MHZ
constant tick :time :=90.4ns; --12MHZ
signal Clock :std_logic; --8051'Clk 12MHZ
begin
-- Unit Under Test port map
UUT : cpldbus51
port map
(Clk => Clk,
Clr => Clr,
P0 => P0,
P2 => P2,
ALE => ALE,
Wr => Wr,
Rd => Rd,
Pina => Pina,
nCS8255 => nCS8255,
RamBank => RamBank,
nCsFlashRam => nCsFlashRam,
FlashRomBank => FlashRomBank );
Reset_p:process
begin
Clr<='1'; --assert
wait for 2000ns;--2Us
Clr<='0';
wait;
end process;
Clock_p:Process --F = 12MHZ
begin
Clock<='0','1' after tick/2;
wait for tick;
end process;
SysClock_p:Process --F = 16MHZ
begin
Clk<='0','1' after Systick/2;
wait for Systick;
end process;
Bus_p:process
begin
Rd<='1';
Wr<='1';
ALE<='0';
P0<="ZZZZZZZZ";
P2<="00000000";
wait for 30*tick;-- wait for reset
-------------------------------------------
--MOVX
--WR
--RAM
---------------------
P0<="ZZZZZZZZ";
--P2<="00000000";
ALE<='1';
wait for tick; --1
P0<="10101010"; --DPL
P2<="01010101"; --DPH
wait for tick; --2
ALE<='0';
wait for 2*tick; --4
P0<="01000011"; --data
wait for tick; --5
Wr<='0';
wait for 6*tick; --11
Wr<='1';
wait for tick; --12
-----------------------------------------
--MOVX
--WR
--RAM
---------------------
P0<="ZZZZZZZZ";
--P2<="00000000";
ALE<='1';
wait for tick; --1
P0<="10101110"; --DPL
P2<="11110101"; --DPH
wait for tick; --2
ALE<='0';
wait for 2*tick; --4
P0<="01001011"; --data
wait for tick; --5
Wr<='0';
wait for 6*tick; --11
Wr<='1';
wait for tick; --12
----------------------------
--MOVX
--WR
--RAM
---------------------
P0<="ZZZZZZZZ";
--P2<="00000000";
ALE<='1';
wait for tick; --1
P0<="10101010"; --DPL
P2<="01010101"; --DPH
wait for tick; --2
ALE<='0';
wait for 2*tick; --4
P0<="01000011"; --data
wait for tick; --5
Wr<='0';
wait for 6*tick; --11
Wr<='1';
wait for tick; --12
----------------------------
--MOVX
--WR
----8255 control reg
---------------------
P0<="ZZZZZZZZ";
--P2<="00000000";
ALE<='1';
wait for tick; --1
P0<="00000011"; --DPL
P2<="11000000"; --DPH
wait for tick; --2
ALE<='0';
wait for 2*tick; --4
P0<="01010011"; --data
wait for tick; --5
Wr<='0';
wait for 6*tick; --11
Wr<='1';
wait for tick; --12
----------------------------
--MOVX
--WR
--RamBankReg
---------------------
P0<="ZZZZZZZZ";
--P2<="00000000";
ALE<='1';
wait for tick; --1
P0<="00000100"; --DPL
P2<="11000000"; --DPH
wait for tick; --2
ALE<='0';
wait for 2*tick; --4
P0<="01000011"; --data
wait for tick; --5
Wr<='0';
wait for 6*tick; --11
Wr<='1';
wait for tick; --12
----------------------------
--MOVX
--WR
--FlashRomBankReg
---------------------
P0<="ZZZZZZZZ";
--P2<="00000000";
ALE<='1';
wait for tick; --1
P0<="00000101"; --DPL
P2<="11000000"; --DPH
wait for tick; --2
ALE<='0';
wait for 2*tick; --4
P0<="01010101"; --data
wait for tick; --5
Wr<='0';
wait for 6*tick; --11
Wr<='1';
wait for tick; --12
----------------------------
--MOVX
--WR
--FlashRom
---------------------
P0<="ZZZZZZZZ";
--P2<="00000000";
ALE<='1';
wait for tick; --1
P0<="00000101"; --DPL
P2<="10000000"; --DPH
wait for tick; --2
ALE<='0';
wait for 2*tick; --4
P0<="11010101"; --data
wait for tick; --5
Wr<='0';
wait for 6*tick; --11
Wr<='1';
wait for tick; --12
----------------------------
--MOVX
--WR
--RAM
---------------------
P0<="ZZZZZZZZ";
--P2<="00000000";
ALE<='1';
wait for tick; --1
P0<="10101011"; --DPL
P2<="01010111"; --DPH
wait for tick; --2
ALE<='0';
wait for 2*tick; --4
P0<="01001011"; --data
wait for tick; --5
Wr<='0';
wait for 6*tick; --11
Wr<='1';
wait for tick; --12
----------------------------
--MOVX
--RD
--
---------------------
P0<="ZZZZZZZZ";
P2<="00000000";
ALE<='1';
wait for tick; --1
P0<="00000100"; --DPL
P2<="11000000"; --DPH
wait for tick; --2
ALE<='0';
wait for 2*tick; --4
P0<="ZZZZZZZZ"; --
wait for tick; --5
P0<="ZZZZZZZZ";
Rd<='0';
wait for 3*tick; --6
--Read the data here please!
wait for tick;
wait for 2*tick;
Rd<='1';
wait for tick; --12
----------------------------
--MOVX
--RD
--
---------------------
P0<="ZZZZZZZZ";
P2<="00000000";
ALE<='1';
wait for tick; --1
P0<="00000101"; --DPL
P2<="11000000"; --DPH
wait for tick; --2
ALE<='0';
wait for 2*tick; --4
P0<="ZZZZZZZZ"; --
wait for tick; --5
P0<="ZZZZZZZZ";
Rd<='0';
wait for 3*tick; --6
--Read the data here please!
wait for tick;
wait for 2*tick;
Rd<='1';
wait for tick; --12
----------------------------
wait ;
end process;
-- --MOVX
-- --RD
-- ---------------------
-- P0<="ZZZZZZZZ";
-- P2<="00000000";
-- ALE<='1';
-- wait for tick; --1
-- P0<="10101010"; --DPL
-- P2<="01010101"; --DPH
-- wait for tick; --2
-- ALE<='0';
-- wait for 2*tick; --4
-- P0<="00000000"; --
-- wait for tick; --5
-- P0<="ZZZZZZZZ";
-- Rd<='0';
-- wait for 3*tick; --6
-- --Read the data here please!
-- wait for tick;
-- wait for 2*tick;
-- Rd<='1';
-- wait for tick; --12
-- ----------------------------
-- --MOVC
-- --PSEN
-- ---------------------
-- P0<="ZZZZZZZZ";
-- P2<="00000000";
-- ALE<='1';
-- PSEN<='1';
-- wait for tick; --1
-- P0<="10101010"; --DPL
-- P2<="01010101"; --DPH
-- wait for tick; --2
-- ALE<='0';
-- wait for tick; --3
-- P0<="ZZZZZZZZ"; --
-- wait for 2*tick;
-- --read the operat code here please!
-- wait for tick;
-- ----------------------------
end TB_ARCHITECTURE;
configuration TESTBENCH_FOR_cpldbus51 of cpldbus51_tb is
for TB_ARCHITECTURE
for UUT : cpldbus51
use entity work.cpldbus51(cpldbus51);
end for;
end for;
end TESTBENCH_FOR_cpldbus51;
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