emit.tan.rpt

这是一个超声波发射的控制电路的设计,可以发出连续的单载波脉冲.

+-------+--------------+------------+------+-------+------------+
; Slack ; Required tco ; Actual tco ; From ; To    ; From Clock ;
+-------+--------------+------------+------+-------+------------+
; N/A   ; None         ; 6.438 ns   ; Q1   ; out_b ; clk1       ;
; N/A   ; None         ; 6.438 ns   ; Q1   ; out_a ; clk1       ;
+-------+--------------+------------+------+-------+------------+


+------------------------------------------------------------+
; tpd                                                        ;
+-------+-------------------+-----------------+------+-------+
; Slack ; Required P2P Time ; Actual P2P Time ; From ; To    ;
+-------+-------------------+-----------------+------+-------+
; N/A   ; None              ; 8.861 ns        ; clk2 ; out_b ;
; N/A   ; None              ; 8.837 ns        ; clk2 ; out_a ;
+-------+-------------------+-----------------+------+-------+


+----------------------------------------------------------------+
; th                                                             ;
+---------------+-------------+-----------+------+----+----------+
; Minimum Slack ; Required th ; Actual th ; From ; To ; To Clock ;
+---------------+-------------+-----------+------+----+----------+
; N/A           ; None        ; 0.138 ns  ; clr1 ; Q1 ; clk1     ;
+---------------+-------------+-----------+------+----+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
    Info: Processing started: Thu Nov 09 20:30:32 2006
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off emit -c emit --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk1" is an undefined clock
Info: Clock "clk1" Internal fmax is restricted to 420.17 MHz between source register "counter_4[0]" and destination register "Q1"
    Info: fmax restricted to clock pin edge rate 2.38 ns. Expand message to see actual delay path.
        Info: + Longest register to register delay is 0.815 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X1_Y4_N1; Fanout = 3; REG Node = 'counter_4[0]'
            Info: 2: + IC(0.311 ns) + CELL(0.420 ns) = 0.731 ns; Loc. = LCCOMB_X1_Y4_N10; Fanout = 1; COMB Node = 'Q1~44'
            Info: 3: + IC(0.000 ns) + CELL(0.084 ns) = 0.815 ns; Loc. = LCFF_X1_Y4_N11; Fanout = 3; REG Node = 'Q1'
            Info: Total cell delay = 0.504 ns ( 61.84 % )
            Info: Total interconnect delay = 0.311 ns ( 38.16 % )
        Info: - Smallest clock skew is 0.000 ns
            Info: + Shortest clock path from clock "clk1" to destination register is 2.631 ns
                Info: 1: + IC(0.000 ns) + CELL(0.959 ns) = 0.959 ns; Loc. = PIN_J2; Fanout = 1; CLK Node = 'clk1'
                Info: 2: + IC(0.218 ns) + CELL(0.000 ns) = 1.177 ns; Loc. = CLKCTRL_G3; Fanout = 3; COMB Node = 'clk1~clkctrl'
                Info: 3: + IC(0.917 ns) + CELL(0.537 ns) = 2.631 ns; Loc. = LCFF_X1_Y4_N11; Fanout = 3; REG Node = 'Q1'
                Info: Total cell delay = 1.496 ns ( 56.86 % )
                Info: Total interconnect delay = 1.135 ns ( 43.14 % )
            Info: - Longest clock path from clock "clk1" to source register is 2.631 ns
                Info: 1: + IC(0.000 ns) + CELL(0.959 ns) = 0.959 ns; Loc. = PIN_J2; Fanout = 1; CLK Node = 'clk1'
                Info: 2: + IC(0.218 ns) + CELL(0.000 ns) = 1.177 ns; Loc. = CLKCTRL_G3; Fanout = 3; COMB Node = 'clk1~clkctrl'
                Info: 3: + IC(0.917 ns) + CELL(0.537 ns) = 2.631 ns; Loc. = LCFF_X1_Y4_N1; Fanout = 3; REG Node = 'counter_4[0]'
                Info: Total cell delay = 1.496 ns ( 56.86 % )
                Info: Total interconnect delay = 1.135 ns ( 43.14 % )
        Info: + Micro clock to output delay of source is 0.250 ns
        Info: + Micro setup delay of destination is -0.036 ns
Info: tsu for register "Q1" (data pin = "clr1", clock pin = "clk1") is 0.092 ns
    Info: + Longest pin to register delay is 2.759 ns
        Info: 1: + IC(0.000 ns) + CELL(0.969 ns) = 0.969 ns; Loc. = PIN_J1; Fanout = 2; PIN Node = 'clr1'
        Info: 2: + IC(1.268 ns) + CELL(0.438 ns) = 2.675 ns; Loc. = LCCOMB_X1_Y4_N10; Fanout = 1; COMB Node = 'Q1~44'
        Info: 3: + IC(0.000 ns) + CELL(0.084 ns) = 2.759 ns; Loc. = LCFF_X1_Y4_N11; Fanout = 3; REG Node = 'Q1'
        Info: Total cell delay = 1.491 ns ( 54.04 % )
        Info: Total interconnect delay = 1.268 ns ( 45.96 % )
    Info: + Micro setup delay of destination is -0.036 ns
    Info: - Shortest clock path from clock "clk1" to destination register is 2.631 ns
        Info: 1: + IC(0.000 ns) + CELL(0.959 ns) = 0.959 ns; Loc. = PIN_J2; Fanout = 1; CLK Node = 'clk1'
        Info: 2: + IC(0.218 ns) + CELL(0.000 ns) = 1.177 ns; Loc. = CLKCTRL_G3; Fanout = 3; COMB Node = 'clk1~clkctrl'
        Info: 3: + IC(0.917 ns) + CELL(0.537 ns) = 2.631 ns; Loc. = LCFF_X1_Y4_N11; Fanout = 3; REG Node = 'Q1'
        Info: Total cell delay = 1.496 ns ( 56.86 % )
        Info: Total interconnect delay = 1.135 ns ( 43.14 % )
Info: tco from clock "clk1" to destination pin "out_b" through register "Q1" is 6.438 ns
    Info: + Longest clock path from clock "clk1" to source register is 2.631 ns
        Info: 1: + IC(0.000 ns) + CELL(0.959 ns) = 0.959 ns; Loc. = PIN_J2; Fanout = 1; CLK Node = 'clk1'
        Info: 2: + IC(0.218 ns) + CELL(0.000 ns) = 1.177 ns; Loc. = CLKCTRL_G3; Fanout = 3; COMB Node = 'clk1~clkctrl'
        Info: 3: + IC(0.917 ns) + CELL(0.537 ns) = 2.631 ns; Loc. = LCFF_X1_Y4_N11; Fanout = 3; REG Node = 'Q1'
        Info: Total cell delay = 1.496 ns ( 56.86 % )
        Info: Total interconnect delay = 1.135 ns ( 43.14 % )
    Info: + Micro clock to output delay of source is 0.250 ns
    Info: + Longest register to pin delay is 3.557 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X1_Y4_N11; Fanout = 3; REG Node = 'Q1'
        Info: 2: + IC(0.313 ns) + CELL(0.150 ns) = 0.463 ns; Loc. = LCCOMB_X1_Y4_N14; Fanout = 1; COMB Node = 'outb~3'
        Info: 3: + IC(0.472 ns) + CELL(2.622 ns) = 3.557 ns; Loc. = PIN_P1; Fanout = 0; PIN Node = 'out_b'
        Info: Total cell delay = 2.772 ns ( 77.93 % )
        Info: Total interconnect delay = 0.785 ns ( 22.07 % )
Info: Longest tpd from source pin "clk2" to destination pin "out_b" is 8.861 ns
    Info: 1: + IC(0.000 ns) + CELL(0.832 ns) = 0.832 ns; Loc. = PIN_N1; Fanout = 2; PIN Node = 'clk2'
    Info: 2: + IC(4.497 ns) + CELL(0.438 ns) = 5.767 ns; Loc. = LCCOMB_X1_Y4_N14; Fanout = 1; COMB Node = 'outb~3'
    Info: 3: + IC(0.472 ns) + CELL(2.622 ns) = 8.861 ns; Loc. = PIN_P1; Fanout = 0; PIN Node = 'out_b'
    Info: Total cell delay = 3.892 ns ( 43.92 % )
    Info: Total interconnect delay = 4.969 ns ( 56.08 % )
Info: th for register "Q1" (data pin = "clr1", clock pin = "clk1") is 0.138 ns
    Info: + Longest clock path from clock "clk1" to destination register is 2.631 ns
        Info: 1: + IC(0.000 ns) + CELL(0.959 ns) = 0.959 ns; Loc. = PIN_J2; Fanout = 1; CLK Node = 'clk1'
        Info: 2: + IC(0.218 ns) + CELL(0.000 ns) = 1.177 ns; Loc. = CLKCTRL_G3; Fanout = 3; COMB Node = 'clk1~clkctrl'
        Info: 3: + IC(0.917 ns) + CELL(0.537 ns) = 2.631 ns; Loc. = LCFF_X1_Y4_N11; Fanout = 3; REG Node = 'Q1'
        Info: Total cell delay = 1.496 ns ( 56.86 % )
        Info: Total interconnect delay = 1.135 ns ( 43.14 % )
    Info: + Micro hold delay of destination is 0.266 ns
    Info: - Shortest pin to register delay is 2.759 ns
        Info: 1: + IC(0.000 ns) + CELL(0.969 ns) = 0.969 ns; Loc. = PIN_J1; Fanout = 2; PIN Node = 'clr1'
        Info: 2: + IC(1.268 ns) + CELL(0.438 ns) = 2.675 ns; Loc. = LCCOMB_X1_Y4_N10; Fanout = 1; COMB Node = 'Q1~44'
        Info: 3: + IC(0.000 ns) + CELL(0.084 ns) = 2.759 ns; Loc. = LCFF_X1_Y4_N11; Fanout = 3; REG Node = 'Q1'
        Info: Total cell delay = 1.491 ns ( 54.04 % )
        Info: Total interconnect delay = 1.268 ns ( 45.96 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
    Info: Processing ended: Thu Nov 09 20:30:32 2006
    Info: Elapsed time: 00:00:01