or2.vhd

来自「《CPLDFPGA嵌入式应用开发技术白金手册》源代码」· VHDL 代码 · 共 15 行

--or2
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
entity or2 is
  port(a,b:in std_logic;
         y:out std_logic);
 end or2;
architecture behav of or2 is
   begin
    y <=a or b;
  end behav;