counter3.vhd

来自「《CPLDFPGA嵌入式应用开发技术白金手册》源代码」· VHDL 代码 · 共 31 行

--counter3 
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity counter3 is
 port(clk,clr:in std_logic;
      bcd:out std_logic_vector(1 downto 0));
end counter3;

architecture rtl of counter3 is
 signal bcdn:std_logic_vector(1 downto 0):="01";--the initial value
  begin
 bcd<=bcdn;
   process(clk)
    begin
  if(clr='0') then
    bcdn<="01";
    else 
      if(clk'event and clk='0') then
       if(bcdn="11") then
        bcdn<="01";
        else
        bcdn<=bcdn+1;
        end if;
       end if;
  end if;
   end process;
 end rtl;