seealarm.vhd

来自「《CPLDFPGA嵌入式应用开发技术白金手册》源代码」· VHDL 代码 · 共 13 行

-- seealarm, conctrol displaying the alarm modle
Library IEEE;
use IEEE.std_logic_1164.all;
entity seealarm is
  port(en:in std_logic;
       norm:in std_logic_vector(1 downto 0);
       q:out std_logic_vector(1 downto 0));
end entity seealarm;
architecture behav of seealarm is
begin
  q<="10" when en='0' else norm;
end behav;