supermux.vhd

来自「《CPLDFPGA嵌入式应用开发技术白金手册》源代码」· VHDL 代码 · 共 25 行

--supermux
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
entity supermux is
  port(q1,q2,q3:in std_logic_vector(3 downto 0);
       sel:in std_logic_vector(1 downto 0);
       chu:out std_logic_vector(3 downto 0));
  end supermux;
architecture rtl of supermux is
 begin
   process(sel)
     begin
 if(sel="00" or sel="11") then
   chu<=q1;
 elsif(sel="01") then
chu<=q2;
 elsif(sel="10") then
 chu<=q3;
end if;
end process;
end rtl;