xor32.vhd

来自「《CPLDFPGA嵌入式应用开发技术白金手册》源代码」· VHDL 代码 · 共 22 行

--xor32
library IEEE;
use IEEE.std_logic_1164.all;
use Ieee.std_logic_unsigned.all;
use Ieee.std_logic_arith.all;
entity  xor32 is
 port(h1,h2,m1,m2,h3,h4,m3,m4:in std_logic_vector(3 downto 0);
       y:out std_logic);
end xor32;
architecture behav of xor32 is
begin
 process(h1,h2,m1,m2,h3,h4,m3,m4)
  begin
   if(h1=h3 and h2=h4 and m1=m3 and m2=m4) then
    y<='0';
   else
    y<='1';
  end if;
  end process;
 end behav;