csout.vhd

来自「《CPLDFPGA嵌入式应用开发技术白金手册》源代码」· VHDL 代码 · 共 21 行

library ieee;
Use ieee.std_logic_1164.all;

Entity csout is
port(data:in std_logic_vector(7 downto 0);
     cs:in std_logic;
     dout:out std_logic_vector(7 downto 0)
     );
end csout;     
Architecture behav of csout is
begin
process(data,cs)
begin
if cs='0' then 
   dout<=data;
else dout<="00000000";
end if;
end process;
end behav;