divider.vhd

来自「《CPLDFPGA嵌入式应用开发技术白金手册》源代码」· VHDL 代码 · 共 27 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;

entity divider is
port(div_in:in std_logic;
     div_cnt:in unsigned(7 downto 0);
     div_out:out std_logic
     );
end divider;

architecture behav of divider is
begin
process
variable cnt:unsigned(7 downto 0);
begin
wait until div_in'event and div_in='1';
    cnt:=cnt+1;
    if cnt=div_cnt then
     div_out<='1';
     cnt:="00000000";
    else div_out<='0';
    end if;
end process;
end behav;