lut.vhd

来自「《CPLDFPGA嵌入式应用开发技术白金手册》源代码」· VHDL 代码 · 共 35 行

library	lpm;
		library	ieee;
		use ieee.std_logic_1164.all;  
		use ieee.std_logic_arith.all;
		use work.mydefine.all;

		entity lut is
		port (addr:in std_logic_vector(rank-1 downto 0);
			outdata:out std_logic_vector(10 downto 0);
			clk:in std_logic);
         end lut;  
		 
		architecture beh of lut is
		component lpm_rom
        generic (LPM_WIDTH : natural;    -- MUST be greater than 0
             LPM_WIDTHAD : natural;    -- MUST be greater than 0
			 LPM_NUMWORDS : natural := 0;
			 LPM_ADDRESS_CONTROL : string := "REGISTERED";
			 LPM_OUTDATA : string := "REGISTERED";
			 LPM_FILE : string;
			 LPM_TYPE : string := "LPM_ROM";
			 LPM_HINT : string := "UNUSED");
	    port (ADDRESS : in STD_LOGIC_VECTOR(LPM_WIDTHAD-1 downto 0);
		    INCLOCK : in STD_LOGIC := '0';
		    OUTCLOCK : in STD_LOGIC := '0';
		    Q : out std_logic_vector(LPM_WIDTH-1 downto 0));
       end component;
	 
	 begin 
		 u1:lpm_rom
		 generic map(11,rank,0,"registered","unregistered","rom.mif","lpm_rom","unused")
         port map(inclock=>clk,address=>addr,q=>outdata);
	end beh;