mul16.vhd

来自「《CPLDFPGA嵌入式应用开发技术白金手册》源代码」· VHDL 代码 · 共 31 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity mul16 is
	port (clk:in std_logic;
		a,b:in std_logic_vector(15 downto 0);
		q:out std_logic_vector(31 downto 0));
end mul16;
architecture beh of mul16 is
	begin
	process (clk)
		variable tmp:std_logic_vector(31 downto 0);
		variable tout:std_logic_vector(31 downto 0);
	begin 
		tout:="00000000000000000000000000000000";
		if (clk'event and clk='1') then
		 for i in 0 to 15 loop
  		  tmp:="00000000000000000000000000000000";
		 if (b(i)='1') then 
  		   for j in 0 to 15 loop 
    	   tmp(i+j):=a(j);
 		   end loop;
         end if;
 		tout:=tmp+tout;
       end loop;
      end if;
   q<=tout;
 end process;
end beh;