mux2_1.vhd

《CPLDFPGA嵌入式应用开发技术白金手册》源代码

--2选1电路方法1
--library ieee;
--use ieee.std_logic_1164.all;
--entity mux2_1 is
  --port(d0,d1,sel:in std_logic;
               --q:out std_logic);
--end mux2_1;
--architecture beh of mux2_1 is
--begin
  --q<=d0 when sel='0' else d1;
--end beh;
--方法2
library ieee;
use ieee.std_logic_1164.all;
entity mux2_1 is
port(d0,d1,sel:in bit;
             q:out bit);
end mux2_1;
architecture lmq of mux2_1 is
begin
  dudu:process(d0,d1,sel)
    variable tmp1,tmp2,tmp3:bit;
  begin
     tmp1:=d0 and sel;
     tmp2:=d1 and (not sel);
     tmp3:=tmp1 or tmp2;
     q<=tmp3;
  end process;
end lmq;