btvid3.c

BT878 图象显示 VxWorks 驱动程序

      MSB_CROP= 0x0000011
      			Set VACTIVE_MSB 01
			Set HACTIVE_MSB 01
			Set HDELAY_MSB and VDELAY_MSB 00

      Hactive=  0x00000140 (320)   Vactive= 0x000001e0 (480)
      Hdelay=   0x0000003c (60)    Vdelay=  0x00000016 (22)
      Hscale=   0x00001555         Vscale=  0x00007e00
	
      Default NTSC values are shown on page 41:
      	Front porch : 21
	HDELAY: 135
	Active: 754
	We want to scale this to 320 active. 754/320 = 2.3562
	If HDELAY and Front porch were scaled by this same value, their
	new values would be:
	Front porch: 21/2.3562=8.91
	HDELAY: 135/2.3562=57.29

	If Hscale is 0x1555 (5461) the total # of pixels would be 
	910/((5461/4096)+1)=390 pixels
	If we make HDELAY 60, this leaves 330 pixels for front porch and
	active region, throwing away 60-57.29 = 2.71 pixels on left.
	Front porch becomes 330-320=10, throwing away 10-8.91=1.09 pixels on right.
	
    	
    */

    PCI_WRITE(MSB_CROP_EVEN_REG,0x0,0x00000011);
    PCI_WRITE(MSB_CROP_ODD_REG,0x0,0x00000011);

    PCI_WRITE(HACTIVE_LO_EVEN_REG,0x0,0x0000002C);
    PCI_WRITE(HACTIVE_LO_ODD_REG,0x0,0x0000002C);
    PCI_WRITE(VACTIVE_LO_EVEN_REG,0x0,0x000000E0);
    PCI_WRITE(VACTIVE_LO_ODD_REG,0x0,0x000000E0);
    PCI_WRITE(VDELAY_LO_EVEN_REG,0x0,0x00000016);
    PCI_WRITE(VDELAY_LO_ODD_REG,0x0,0x00000016);
    PCI_WRITE(HDELAY_LO_EVEN_REG,0x0,0x00000046);
    PCI_WRITE(HDELAY_LO_ODD_REG,0x0,0x00000046);

    /* Set HSCALE for 320 pixels per line */
    PCI_WRITE(HSCALE_EVEN_MSB_REG,0x0,0x00000015);
    PCI_WRITE(HSCALE_ODD_MSB_REG,0x0,0x00000015);
    PCI_WRITE(HSCALE_EVEN_LSB_REG,0x0,0x00000055);
    PCI_WRITE(HSCALE_ODD_LSB_REG,0x0,0x00000055);

    /* Set VSCALE for 240 lines per frame */
    PCI_WRITE(VSCALE_EVEN_MSB_REG,0x0,0x0000007E);
    PCI_WRITE(VSCALE_ODD_MSB_REG,0x0,0x0000007E);
    PCI_WRITE(VSCALE_EVEN_LSB_REG,0x0,0x00000000);
    PCI_WRITE(VSCALE_ODD_LSB_REG,0x0,0x00000000);

    PCI_WRITE(COLOR_FORMAT_REG,0x0,0x00000066);
    acq_type = NTSC_320_X_240_GS;
  }

  else if(fsize==NTSC_80_X_60)
  {
    /*

      Set up the delay and active registers so that they cover
      full resolution.

      Scaled pixels / line = 81

      Crop 0.79 on left for 80 pixels / line

      For 80X60, want:

      MSB_CROP= 0x0000000

      Hactive=  0x00000050 (80)   Vactive=  0x000001e0 (480)
      Hdelay=   0x00000010 (16)    Vdelay=  0x00000016 (22)
      Hscale=   0x0000861A         Vscale=  0x00007200

    */

    PCI_WRITE(MSB_CROP_EVEN_REG,0x0,0x00000010);
    PCI_WRITE(MSB_CROP_ODD_REG,0x0, 0x00000010);

    PCI_WRITE(HACTIVE_LO_EVEN_REG,0x0,0x00000050);
    PCI_WRITE(HACTIVE_LO_ODD_REG,0x0,0x00000050);
    PCI_WRITE(VACTIVE_LO_EVEN_REG,0x0,0x000000E0);
    PCI_WRITE(VACTIVE_LO_ODD_REG,0x0,0x000000E0);
    PCI_WRITE(VDELAY_LO_EVEN_REG,0x0,0x00000016);
    PCI_WRITE(VDELAY_LO_ODD_REG,0x0,0x00000016);
    PCI_WRITE(HDELAY_LO_EVEN_REG,0x0,0x00000010);
    PCI_WRITE(HDELAY_LO_ODD_REG,0x0,0x00000010);

    /* Set HSCALE for 320 pixels per line */
    PCI_WRITE(HSCALE_EVEN_MSB_REG,0x0,0x00000086);
    PCI_WRITE(HSCALE_ODD_MSB_REG,0x0,0x00000086);
    PCI_WRITE(HSCALE_EVEN_LSB_REG,0x0,0x0000001A);
    PCI_WRITE(HSCALE_ODD_LSB_REG,0x0,0x0000001A);

    /* Set VSCALE for 240 lines per frame */
    PCI_WRITE(VSCALE_EVEN_MSB_REG,0x0,0x00000072);
    PCI_WRITE(VSCALE_ODD_MSB_REG,0x0,0x00000072);
    PCI_WRITE(VSCALE_EVEN_LSB_REG,0x0,0x00000000);
    PCI_WRITE(VSCALE_ODD_LSB_REG,0x0,0x00000000);

    /* Set color format for Y8 GRAYSCALE on ODD and EVEN */
    PCI_WRITE(COLOR_FORMAT_REG,0x0,0x00000066);

  }

  else if(fsize==NTSC_640_X_480)
  {


    /*

      Set up the delay and active registers so that they cover
      full resolution.

      Scaled pixels / line = 646

      Crop 4 on left, 2 on right for 640 pixels / line

      For 640x480, want:

      MSB_CROP= 0x0000012

      Hactive= 0x00000280 (640)    Vactive= 0x000001e0 (480)
      Hdelay=  0x00000078 (120)    Vdelay=  0x00000016 (22)
      Hscale=  0x000002aa          Vscale=  0x00006000

    */

    PCI_WRITE(MSB_CROP_EVEN_REG,0x0,0x00000012);
    PCI_WRITE(MSB_CROP_ODD_REG,0x0,0x00000012);

    PCI_WRITE(HACTIVE_LO_EVEN_REG,0x0,0x00000080);
    PCI_WRITE(HACTIVE_LO_ODD_REG,0x0,0x00000080);
    PCI_WRITE(VACTIVE_LO_EVEN_REG,0x0,0x000000E0);
    PCI_WRITE(VACTIVE_LO_ODD_REG,0x0,0x000000E0);
    PCI_WRITE(VDELAY_LO_EVEN_REG,0x0,0x00000016);
    PCI_WRITE(VDELAY_LO_ODD_REG,0x0,0x00000016);
    PCI_WRITE(HDELAY_LO_EVEN_REG,0x0,0x00000078);
    PCI_WRITE(HDELAY_LO_ODD_REG,0x0,0x00000078);

    /* Set HSCALE for 640 pixels per line */
    PCI_WRITE(HSCALE_EVEN_MSB_REG,0x0,0x00000002);
    PCI_WRITE(HSCALE_ODD_MSB_REG,0x0,0x00000002);
    PCI_WRITE(HSCALE_EVEN_LSB_REG,0x0,0x000000AA);
    PCI_WRITE(HSCALE_ODD_LSB_REG,0x0,0x000000AA);

    /* Set VSCALE for 480 lines per frame */
    PCI_WRITE(VSCALE_EVEN_MSB_REG,0x0,0x00000060);
    PCI_WRITE(VSCALE_ODD_MSB_REG,0x0,0x00000060);
    PCI_WRITE(VSCALE_EVEN_LSB_REG,0x0,0x00000000);
    PCI_WRITE(VSCALE_ODD_LSB_REG,0x0,0x00000000);


    /* Set color format for RGB32 on ODD and EVEN */
    PCI_WRITE(COLOR_FORMAT_REG,0x0,0x00000000);
  }

  /* Enable the DMA RISC instruction IRQ */ 
  PCI_WRITE(INT_ENABLE_REG,0x0,(int_errors_to_check|RISCI_INT|VPRES_INT));

  /* Reduce frame rate from max of 30 frames/sec or 60 fields/sec */
  PCI_WRITE(TEMP_DECIMATION_REG,0x0,0x00000000);  /* reset */
  PCI_WRITE(TEMP_DECIMATION_REG,0x0,0x00000000);  /* set */

}


int decimate_frames(int count)
{
  unsigned int fcnt = count;

  if(count > 60 || count < 0)
    return -1;

  else
  {
    /* Reduce frame rate from max of 30 frames/sec */
    PCI_WRITE(TEMP_DECIMATION_REG,0x0,0x00000000);  /* reset */
    PCI_WRITE(TEMP_DECIMATION_REG,0x0,fcnt);  /* set */

    return count;
  }

}


void disable_capture(void)
{
  PCI_WRITE(CAPTURE_CTL_REG,0x0,0x00000000);
}


void enable_capture(void)
{
  vdfc_capture();
}


void set_brightness(int b)
{
  int bright;
  unsigned int hb;

  PCI_READ(BRIGHTNESS_REG,0x0,&hb);

  if(hb < 0x7f)
    bright = hb + 0x80;
  else
    bright = hb - 0x7f;

  printf("Brightness was %d\n", bright);

  if(b > 255)
    b = 255;
  else if(b < 0)
    b = 0;

  bright = b + 0x80;

  if(bright > 0xFF)
    bright = bright - 0xFF;

  hb = bright;

  PCI_WRITE(BRIGHTNESS_REG,0x0,hb);

}


void set_contrast(int c)
{
  int contrast;
  unsigned int hc;

  PCI_READ(CONTRAST_REG,0x0,&hc);

  if(hc < 0x7f)
    contrast = hc + 0x80;
  else
    contrast = hc - 0x7f;

  printf("Contrast was %d\n", contrast);

  if(c > 255)
    c = 255;
  else if(c < 0)
    c = 0;

  contrast = c + 0x80;

  if(contrast > 0xFF)
    contrast = contrast - 0xFF;

  hc = contrast;

  PCI_WRITE(CONTRAST_REG,0x0,hc);

}


void vdfc_capture(void)
{
  /* Set the video capture control -- ODD and EVEN through VFDC */
  PCI_WRITE(CAPTURE_CTL_REG,0x0,0x00000013);
}


void vbi_capture(void)
{

  /* Set the video capture control -- ODD and EVEN VBI 

     Given NTSC full resolution frame format of:

      9   VSYNC           1          9
     11   VBI            10         20    -- Vertical Blanking Interval
    242.5 ODD            21        263.5
      9   VSYNC         263.5      272.5
     11   VBI           272.5      283.5  -- Vertical Blanking Interval
    242.5 EVEN          283.5      525
    -------------------------------------
    525

    
   */

  /**** Enable VBI Capture ****/
  PCI_WRITE(CAPTURE_CTL_REG,0x0,0x0000001C);

 
  /**** Standard VBI ****/ 
  PCI_WRITE(VBI_PACKET_SIZE_LO_REG,0x0,0x0000000B);
  PCI_WRITE(VBI_PACKET_SIZE_HI_REG,0x0,0x00000000);

}


void load_test_mc(int mc)
{
  if(mc == TEST_MICROCODE)
  {
    initialize_test_mc();
    PCI_WRITE(DMA_RISC_START_ADDR_REG,0x0,(unsigned int)&(dma_test_microcode[0]));
  }
  else
  {
    printf("Bad test MC\n");
  }
}


void load_frame_mc(int fsize)
{
  initialize_frame_mc(fsize);

  if((fsize==NTSC_320_X_240) || (fsize==NTSC_320_X_240_GS))
    PCI_WRITE(DMA_RISC_START_ADDR_REG,0x0,(unsigned int)&(dma_microcode[0]));
  else if(fsize==NTSC_80_X_60)
    PCI_WRITE(DMA_RISC_START_ADDR_REG,0x0,(unsigned int)&(dma_puny_microcode[0]));
  else if(fsize==NTSC_640_X_480)
    PCI_WRITE(DMA_RISC_START_ADDR_REG,0x0,(unsigned int)&(dma_large_microcode[0]));
}


void sw_reset(void)
{
  PCI_WRITE(RESET_REG,0x0,0x00000001);
}


void toggle_fifo(int t)
{
  unsigned int testval;

  PCI_READ(DMA_CTL_REG,0x0,&testval);

  if(t)
  {
    /* Enable FIFO */
    testval = testval | 0x00000001;
  }
  else
  {
    /* Disable FIFO */
    testval = testval & 0xFFFFFFFE;
  }

  PCI_WRITE(DMA_CTL_REG,0x0,testval);
}


void toggle_dma(int t)
{
  unsigned int testval;

  PCI_READ(DMA_CTL_REG,0x0,&testval);

  if(t)
  {
    /* Enable DMA */
    testval = testval | 0x00000002;
  }
  else
  {
    /* Disable DMA */
    testval = testval & 0xFFFFFFFD;
  }

  PCI_WRITE(DMA_CTL_REG,0x0,testval);

}


void start_acq(void)
{
  /* Enable DMA and data FIFO 

     The packed trigger point is set to max.

   */
  PCI_WRITE(DMA_CTL_REG,0x0,0x0000000F);
}


void halt_acq(void)
{
  /* Disable DMA and data FIFO */
  PCI_WRITE(DMA_CTL_REG,0x0,0x00000000);
}



void pci_inta_isr(int param)
{

	/*logMsg("Int!\n",0,0,0,0,0,0);*/

  total_ints++;

  PCI_READ(INT_STATUS_REG,0x0,&last_isr_status);

  /* Clear the INTA interrupt status 

     Clear ALL RR bits:
     PCI_WRITE(INT_STATUS_REG,0x0,0x000FFB3F);

   */
  PCI_WRITE(INT_STATUS_REG,0x0,last_isr_status);


  if(last_isr_status & int_errors_to_check)
  {

    /* Did error halt the DMA? */
    if(last_isr_status & 0x08000000)
      total_dma_disabled_errs++;

    halt_acq();

    start_acq();


    if(last_isr_status & SCERR_INT)
    {
      total_sync_errs++;
      halt_acq();
      start_acq();
    }

    if(last_isr_status & OCERR_INT)
    {
      total_dma_errs++;
      halt_acq();
      start_acq();
    }

    if(last_isr_status & PABORT_INT)
      total_abort_errs++;

    if(last_isr_status & RIPERR_INT)
      total_parity_errs++;

    if(last_isr_status & PPERR_INT)
      total_bus_parity_errs++;

    if(last_isr_status & FDSR_INT)
      total_fifo_resync_errs++;

    if(last_isr_status & FTRGT_INT)
      total_fifo_overrun_errs++;

    if(last_isr_status & FBUS_INT)
      total_bus_latency_errs++;

  }

  
  else if(last_isr_status & RISCI_INT)
  {
    total_risc_ints++;

    if(last_isr_status & (DMA_MC_WRITE<<12))
      total_write_tags++;

    if(last_isr_status & (DMA_MC_SKIP<<12))
      total_skip_tags++;

    if(last_isr_status & (DMA_MC_JUMP<<12))
      total_jump_tags++;

    if(last_isr_status & (DMA_MC_SYNC<<12))
      total_sync_tags++;

    /* Bump the frame_acq_cnt */
    frame_acq_cnt++;

    current_frame = !current_frame;

    /* Notify client that frame is ready */
    semGive(frameRdy);

    /* Check the device status */
    PCI_READ(BTVID_MMIO_ADDR,0x0,&last_dstatus);
  }


}


void full_reset(void)
{

  halt_acq();

  disable_capture();

  taskDelete(btvid_tid);

  frame_acq_cnt = 0;
  frame_rdy_cnt = 0;
  last_dstatus = 0x0;
  last_isr_status = 0x0;
  total_dma_disabled_errs = 0x0;
  total_sync_errs = 0x0;
  total_abort_errs = 0x0;
  total_dma_errs = 0x0;
  total_parity_errs = 0x0;
  total_bus_parity_errs = 0x0;
  total_fifo_overrun_errs = 0x0;
  total_fifo_resync_errs = 0x0;
  total_bus_latency_errs = 0x0;
  total_risc_ints = 0x0;
  total_write_tags = 0x0;
  total_skip_tags = 0x0;
  total_jump_tags = 0x0;
  total_sync_tags = 0x0;

  semDelete(frameRdy);

  sw_reset();

  intel_pci_clear_status();

  reset_status();

}



void activate(int fsize)
{
  test_status();

  connect_pci_int(BT878INT);

  sysIntEnablePIC(BT878INT);

  configure_ntsc(fsize);
  logMsg("Configured NTSC\n",0,0,0,0,0,0);

  set_mux(1);
  logMsg("Set mux\n",0,0,0,0,0,0);

  load_frame_mc(fsize);
  printf("Loaded MC\n");
  clear_buffers(fsize);
  enable_capture();
  start_acq();

  test_status();
}


void activate_test(int mc)
{
  test_status();

  connect_pci_int(BT878INT);
  sysIntEnablePIC(BT878INT);

  configure_ntsc(1);

  set_mux(1);

  load_test_mc(mc);
  clear_buffers(2);
  enable_capture();
  start_acq();


  test_status();
}


void connect_pci_int(int inum)
{

  pciIntConnect((INUM_TO_IVEC (inum+INT_NUM_IRQ0)), (VOIDFUNCPTR)pci_inta_isr, 0);