📄 main.lst
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ARM COMPILER V2.51, main 04/04/06 09:59:06 PAGE 1
ARM COMPILER V2.51, COMPILATION OF MODULE main
OBJECT MODULE PLACED IN main.OBJ
COMPILER INVOKED BY: C:\Keil\ARM\BIN\CA.exe main.c THUMB BROWSE DEBUG TABS(4)
stmt level source
1 #include <LPC21xx.H>
2
3
4 void SPI_ISR (void) __irq;
5 void SPI_write(unsigned char *buffer,unsigned char bytecount);
6 void SPI_read(unsigned char *buffer,unsigned char bytecount);
7
8 unsigned char status = 0;
9 unsigned char SPI_bytecount = 0;
10 unsigned char * SPI_buffer;
11 volatile unsigned char lock = 0;
12 unsigned char input_buffer[8];
13 void main (void)
14 {
15 1 unsigned char output_buffer[8] = {1,2,3,4,5,6,7,8};
16 1
17 1
18 1
19 1 PINSEL0 = 0x00005500; //Enable SPI0 pins
20 1 IODIR0 = 0x00000400; //Enable Chipselect pin as output
21 1
22 1 S0SPCCR = 0x000000FF; //Set bit timing
23 1 S0SPCR = 0x000000A0; //Configure as SPI Master interrupts enabled
24 1
25 1
26 1 VICVectCntl0 = 0x0000002A; //Select a priority slot for a given interrupt
27 1 VICVectAddr0 = (unsigned)SPI_ISR; //Pass the address of the IRQ into the VIC slot
28 1 VICIntEnable = 0x00000400; //Enable interrupt
29 1
30 1 SPI_write(output_buffer,8); //Write eight bytes to the memory
31 1 while(lock)
32 1 {
33 2 ;
34 2 }
35 1 SPI_read(input_buffer,8); //Read them back
36 1 IOCLR0 = input_buffer[0];
37 1
38 1 while(1)
39 1 {
40 2 ;
41 2 }
42 1 }
43
44
45 void SPI_write(unsigned char *buffer,unsigned char bytecount)
46 {
47 1 lock = 1;
48 1 SPI_buffer = buffer;
49 1 SPI_bytecount = bytecount;
50 1 IOCLR0 = 0x00000400; //Pull Chipselect low
51 1 S0SPDR = 0x00000006; //Send WRITE opcode
52 1 status = 0x01; //set next state
53 1 }
54
55 void SPI_read(unsigned char *buffer,unsigned char bytecount)
56 {
57 1 SPI_buffer = buffer;
58 1 SPI_bytecount = bytecount;
59 1 IOCLR0 = 0x00000400; //Pull Chipselect low
ARM COMPILER V2.51, main 04/04/06 09:59:06 PAGE 2
60 1 S0SPDR = 0x00000003; //Send READ code
61 1 status = 0x05; //set next state
62 1 }
63
64
65 void SPI_ISR (void) __irq
66 {
67 1 unsigned char result;
68 1 unsigned int test;
69 1
70 1 switch(status)
71 1 {
72 2 case (0x01):
73 2 //Send Write opcode
74 2 S0SPDR = 0x00000002;
75 2 status = 0x02; //set next state
76 2 break;
77 2
78 2 case (0x02): //Send Write Address
79 2 S0SPDR = 0x00000000;
80 2 status = 0x03; //Set next state
81 2 break;
82 2
83 2 case (0x03): //write data
84 2 S0SPDR = *SPI_buffer++;
85 2 if( --SPI_bytecount)
86 2 {
87 3 status = 0x03; //Set Next state
88 3 }
89 2 else
90 2 {
91 3 status = 0x04; //End condition
92 3 }
93 2 break;
94 2
95 2 case (0x04): //End condition
96 2 S0SPDR = 0x00000055; //Need this dummy write for simulation
97 2 IOSET0 = 0x00000400; //Pull Chipselect high
98 2 status = 0x07; //jump to null case
99 2 break;
100 2
101 2
102 2 case (0x05):
103 2 S0SPDR = 0x00000000; //Send Address
104 2 status = 0x06; //set next state
105 2 break;
106 2
107 2 case (0x06):
108 2 *SPI_buffer = S0SPDR; //read data
109 2 S0SPDR = 0xFF; //Send Address
110 2 SPI_buffer++;
111 2
112 2 if( --SPI_bytecount)
113 2 {
114 3 status = 0x06; //Set Next state
115 3 }
116 2 else
117 2 {
118 3 status = 0x07; //End condition
119 3 }
120 2 break;
121 2
122 2 case (0x07) : //Null Case
123 2 lock = 0;
124 2 break;
125 2
ARM COMPILER V2.51, main 04/04/06 09:59:06 PAGE 3
126 2 default :
127 2 break;
128 2
129 2 }
130 1
131 1 S0SPINT = 0x01; //Signal end of interrupt
132 1 VICVectAddr = 0x00000000; //Dummy write to signal end of interrupt
133 1 }
*** WARNING C47 IN LINE 67 OF MAIN.C: 'result': unreferenced local variable
*** WARNING C47 IN LINE 68 OF MAIN.C: 'test': unreferenced local variable
ARM COMPILER V2.51, main 04/04/06 09:59:06 PAGE 4
ASSEMBLY LISTING OF GENERATED OBJECT CODE
*** EXTERNALS:
EXTERN NUMBER (__startup)
*** PUBLICS:
PUBLIC SPI_ISR?A
PUBLIC SPI_write?T
PUBLIC SPI_read?T
PUBLIC main
PUBLIC status
PUBLIC SPI_bytecount
PUBLIC SPI_buffer
PUBLIC lock
PUBLIC input_buffer
*** DATA SEGMENT '?DT0?main':
00000000 SPI_buffer:
00000000 DS 4
00000004 status:
00000004 BEGIN_INIT
00000004 00 DB 0x0
00000005 END_INIT
00000005 SPI_bytecount:
00000005 BEGIN_INIT
00000005 00 DB 0x0
00000006 END_INIT
00000006 lock:
00000006 BEGIN_INIT
00000006 00 DB 0x0
00000007 END_INIT
00000007 input_buffer:
00000007 DS 8
*** DATA SEGMENT '?CON?main':
00000000 ?tpl?0001:
00000000 BEGIN_INIT
00000000 01 DB 0x1
00000001 02 DB 0x2
00000002 03 DB 0x3
00000003 04 DB 0x4
00000004 05 DB 0x5
00000005 06 DB 0x6
00000006 07 DB 0x7
00000007 08 DB 0x8
00000008 END_INIT
*** CODE SEGMENT '?PR?main?main':
13: void main (void)
00000000 B500 PUSH {LR}
00000002 B082 SUB R13,#0x8
14: {
00000004 ; SCOPE-START
15: unsigned char output_buffer[8] = {1,2,3,4,5,6,7,8};
00000004 4800 LDR R1,=?tpl?0001 ; ?tpl?0001
00000006 A800 ADD R0,R13,#0x0
00000008 2208 MOV R2,#0x8
0000000A L_23:
0000000A 780B LDRB R3,[R1,#0x0]
0000000C 7003 STRB R3,[R0,#0x0]
0000000E 1C49 ADD R1,R1,#0x1
00000010 1C40 ADD R0,R0,#0x1
00000012 1E52 SUB R2,R2,#0x1
00000014 D1F9 BNE L_23 ; T=0x0000000A
19: PINSEL0 = 0x00005500; //Enable SPI0 pins
00000016 4800 LDR R1,=0x5500
ARM COMPILER V2.51, main 04/04/06 09:59:06 PAGE 5
00000018 4800 LDR R0,=0xE002C000
0000001A 6001 STR R1,[R0,#0x0]
20: IODIR0 = 0x00000400; //Enable Chipselect pin as output
0000001C 4800 LDR R1,=0x400
0000001E 4800 LDR R0,=0xE0028008
00000020 6001 STR R1,[R0,#0x0]
22: S0SPCCR = 0x000000FF; //Set bit timing
00000022 22FF MOV R2,#0xFF
00000024 4800 LDR R0,=0xE002000C
00000026 7002 STRB R2,[R0,#0x0]
23: S0SPCR = 0x000000A0; //Configure as SPI Master interrupts enabled
00000028 22A0 MOV R2,#0xA0
0000002A 4800 LDR R0,=0xE0020000
0000002C 7002 STRB R2,[R0,#0x0]
26: VICVectCntl0 = 0x0000002A; //Select a priority slot for a given interrupt
0000002E 222A MOV R2,#0x2A
00000030 4800 LDR R0,=0xFFFFF200
00000032 6002 STR R2,[R0,#0x0]
27: VICVectAddr0 = (unsigned)SPI_ISR; //Pass the address of the IRQ into the VIC slot
00000034 4A00 LDR R2,=SPI_ISR?A ; SPI_ISR?A
00000036 4800 LDR R0,=0xFFFFF100
00000038 6002 STR R2,[R0,#0x0]
28: VICIntEnable = 0x00000400; //Enable interrupt
0000003A 4800 LDR R0,=0xFFFFF010
0000003C 6001 STR R1,[R0,#0x0]
30: SPI_write(output_buffer,8); //Write eight bytes to the memory
0000003E A800 ADD R0,R13,#0x0
00000040 2108 MOV R1,#0x8
00000042 F7FF BL SPI_write?T ; T=0x0001 (1)
00000044 FFDD BL SPI_write?T ; T=0x0001 (2)
34: }
00000046 L_1:
00000046 4800 LDR R0,=lock ; lock
00000048 7800 LDRB R0,[R0,#0x0] ; lock
0000004A 2800 CMP R0,#0x0
0000004C D1FB BNE L_1 ; T=0x00000046
35: SPI_read(input_buffer,8); //Read them back
0000004E 4800 LDR R0,=input_buffer ; input_buffer
00000050 2108 MOV R1,#0x8
00000052 F7FF BL SPI_read?T ; T=0x0001 (1)
00000054 FFD5 BL SPI_read?T ; T=0x0001 (2)
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