📄 nestint.cod
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LA ARM LINKER/LOCATER V0.21 11/18/2004 14:06:02 PAGE 1
ASSEMBLER CODE LISTING OF MODULE: NestInt (STARTUP)
*** Disassembly of Segment '?C_CLRSEG':
00000110 40000490 DD ?DT0?Intrp
00000114 4000049C DD ?DT0?Intrp + 0xC
00000118 00000000 DD 0x0
0000011C 00000000 DD 0x0
*** Disassembly of Segment '?C_INITSEG':
00000120 00000000 DD 0x0
00000124 00000000 DD 0x0
*** Disassembly of Segment 'STACK':
51: DS (USR_Stack_Size+3)&~3 ; Stack for User/System Mode
40000000 DS 1024
52: DS (IRQ_Stack_Size+3)&~3 ; Stack for Interrupt Mode
40000400 DS 128
53: DS (FIQ_Stack_Size+3)&~3 ; Stack for Fast Interrupt Mode
40000480 DS 4
54: DS (ABT_Stack_Size+3)&~3 ; Stack for Abort Mode
40000484 DS 4
55: DS (SVC_Stack_Size+3)&~3 ; Stack for Supervisor Mode
40000488 DS 4
56: DS (UND_Stack_Size+3)&~3 ; Stack for Undefined Mode
4000048C DS 4
57: Top_Stack:
40000490 Top_Stack:
*** Disassembly of Segment '?DT0?Intrp':
12: int volatile intrp_count = 0;
40000490 ALIGN 4
40000490 intrp_count:
40000490 DS 4
13: int volatile timeval = 0;
40000494 ALIGN 4
40000494 timeval:
40000494 DS 4
14: int volatile SecondCnt = 0;
40000498 ALIGN 4
40000498 SecondCnt:
40000498 DS 4
*** Disassembly of Segment 'STARTUPCODE':
FILE: 'Startup.s'
207: __startup PROC CODE32
00000000 ; SCOPE-START
222: Vectors: LDR PC,Reset_Addr
00000000 Vectors:
00000000 E59FF018 LDR R15,[R15,#Reset_Addr]
223: LDR PC,Undef_Addr
00000004 E59FF018 LDR R15,[R15,#Undef_Addr]
224: LDR PC,SWI_Addr
00000008 E59FF018 LDR R15,[R15,#SWI_Addr]
225: LDR PC,PAbt_Addr
0000000C E59FF018 LDR R15,[R15,#PAbt_Addr]
226: LDR PC,DAbt_Addr
00000010 E59FF018 LDR R15,[R15,#DAbt_Addr]
227: NOP /* Reserved Vector */
00000014 E1A00000 NOP
229: LDR PC,[PC, #-0x0FF0] /* Vector from VicVectAddr */
00000018 E51FFFF0 LDR R15,[R15,#-0xFF0]
LA ARM LINKER/LOCATER V0.21 11/18/2004 14:06:02 PAGE 2
230: LDR PC,FIQ_Addr
0000001C E59FF018 LDR R15,[R15,#FIQ_Addr]
232: Reset_Addr: DD Reset_Handler
00000020 Reset_Addr:
00000020 00000040 DD Reset_Handler
233: Undef_Addr: DD Undef_Handler?A
00000024 Undef_Addr:
00000024 00000378 DD Undef_Handler?A
234: SWI_Addr: DD SWI_Handler?A
00000028 SWI_Addr:
00000028 00000374 DD SWI_Handler?A
235: PAbt_Addr: DD PAbt_Handler?A
0000002C PAbt_Addr:
0000002C 00000370 DD PAbt_Handler?A
236: DAbt_Addr: DD DAbt_Handler?A
00000030 DAbt_Addr:
00000030 0000036C DD DAbt_Handler?A
237: DD 0 /* Reserved Address */
00000034 00000000 DD 0x0
238: IRQ_Addr: DD IRQ_Handler?A
00000038 IRQ_Addr:
00000038 00000368 DD IRQ_Handler?A
239: FIQ_Addr: DD FIQ_Handler?A
0000003C FIQ_Addr:
0000003C 00000364 DD FIQ_Handler?A
244: Reset_Handler:
00000040 Reset_Handler:
281: LDR R0, =PLL_BASE
00000040 E59F00B0 MOV R0,[PC,+176] ; PoolRef @0xF8
282: MOV R1, #0xAA
00000044 E3A010AA MOV R1,#0x00AA
283: MOV R2, #0x55
00000048 E3A02055 MOV R2,#0x0055
286: MOV R3, #PLLCFG_Val
0000004C E3A03024 MOV R3,#0x0024
287: STR R3, [R0, #PLLCFG_OFS]
00000050 E5803004 STR R3,[R0,#PLLCFG_OFS]
288: MOV R3, #PLLCON_PLLE
00000054 E3A03001 MOV R3,#0x0001
289: STR R3, [R0, #PLLCON_OFS]
00000058 E5803000 STR R3,[R0,#PLLCON_OFS]
290: STR R1, [R0, #PLLFEED_OFS]
0000005C E580100C STR R1,[R0,#PLLFEED_OFS]
291: STR R2, [R0, #PLLFEED_OFS]
00000060 E580200C STR R2,[R0,#PLLFEED_OFS]
294: PLL_Loop: LDR R3, [R0, #PLLSTAT_OFS]
00000064 PLL_Loop:
00000064 E5903008 LDR R3,[R0,#PLLSTAT_OFS]
295: ANDS R3, R3, #PLLSTAT_PLOCK
00000068 E2133B01 ANDS R3,R3,#0x0400
296: BEQ PLL_Loop
0000006C 0AFFFFFC BEQ PLL_Loop ; Targ=0x64
299: MOV R3, #(PLLCON_PLLE | PLLCON_PLLC)
00000070 E3A03003 MOV R3,#0x0003
300: STR R3, [R0, #PLLCON_OFS]
00000074 E5803000 STR R3,[R0,#PLLCON_OFS]
301: STR R1, [R0, #PLLFEED_OFS]
00000078 E580100C STR R1,[R0,#PLLFEED_OFS]
302: STR R2, [R0, #PLLFEED_OFS]
0000007C E580200C STR R2,[R0,#PLLFEED_OFS]
307: LDR R0, =MAM_BASE
00000080 E59F0074 MOV R0,[PC,+116] ; PoolRef @0xFC
308: MOV R1, #MAMTIM_Val
00000084 E3A01004 MOV R1,#0x0004
309: STR R1, [R0, #MAMTIM_OFS]
LA ARM LINKER/LOCATER V0.21 11/18/2004 14:06:02 PAGE 3
00000088 E5801004 STR R1,[R0,#MAMTIM_OFS]
310: MOV R1, #MAMCR_Val
0000008C E3A01002 MOV R1,#0x0002
311: STR R1, [R0, #MAMCR_OFS]
00000090 E5801000 STR R1,[R0,#MAMCR_OFS]
326: LDR R0, =Top_Stack
00000094 E59F0064 MOV R0,[PC,+100] ; PoolRef @0x100
329: MSR CPSR_c, #Mode_UND|I_Bit|F_Bit
00000098 E321F0DB MSR CPSR_c,#0xDB
330: MOV SP, R0
0000009C E1A0D000 MOV R13,R0
331: SUB R0, R0, #UND_Stack_Size
000000A0 E2400004 SUB R0,R0,#0x0004
334: MSR CPSR_c, #Mode_ABT|I_Bit|F_Bit
000000A4 E321F0D7 MSR CPSR_c,#0xD7
335: MOV SP, R0
000000A8 E1A0D000 MOV R13,R0
336: SUB R0, R0, #ABT_Stack_Size
000000AC E2400004 SUB R0,R0,#0x0004
339: MSR CPSR_c, #Mode_FIQ|I_Bit|F_Bit
000000B0 E321F0D1 MSR CPSR_c,#0xD1
340: MOV SP, R0
000000B4 E1A0D000 MOV R13,R0
341: SUB R0, R0, #FIQ_Stack_Size
000000B8 E2400004 SUB R0,R0,#0x0004
344: MSR CPSR_c, #Mode_IRQ|I_Bit|F_Bit
000000BC E321F0D2 MSR CPSR_c,#0xD2
345: MOV SP, R0
000000C0 E1A0D000 MOV R13,R0
346: SUB R0, R0, #IRQ_Stack_Size
000000C4 E2400080 SUB R0,R0,#0x0080
349: MSR CPSR_c, #Mode_SVC|I_Bit|F_Bit
000000C8 E321F0D3 MSR CPSR_c,#0xD3
350: MOV SP, R0
000000CC E1A0D000 MOV R13,R0
351: SUB R0, R0, #SVC_Stack_Size
000000D0 E2400004 SUB R0,R0,#0x0004
354: MSR CPSR_c, #Mode_USR
000000D4 E321F010 MSR CPSR_c,#Mode_USR
355: MOV SP, R0
000000D8 E1A0D000 MOV R13,R0
358: LDR R0,=?C?INIT
000000DC E59F0020 MOV R0,[PC,+32] ; PoolRef @0x104
359: TST R0,#1 ; Bit-0 set: INIT is Thumb
000000E0 E3100001 TST R0,#0x0001
360: LDREQ LR,=exit?A ; ARM Mode
000000E4 059FE01C MOVEQ R14,[PC,+28] ; PoolRef @0x108
361: LDRNE LR,=exit?T ; Thumb Mode
000000E8 159FE01C MOVNE R14,[PC,+28] ; PoolRef @0x10C
362: BX R0
000000EC E12FFF10 BX R0
363: ENDP
000000F0 ; SCOPE-END
366: exit?A PROC CODE32
000000F0 ; SCOPE-START
367: B exit?A
000000F0 EAFFFFFE B exit?A ; Targ=0xF0
368: ENDP
000000F4 ; SCOPE-END
371: exit?T PROC CODE16
000000F4 ; SCOPE-START
372: exit: B exit?T
000000F4 exit:
000000F4 E7FE B exit?T ; T=0x000000F4
373: ENDP
LA ARM LINKER/LOCATER V0.21 11/18/2004 14:06:02 PAGE 4
000000F6 ; SCOPE-END
000000F6 ALIGN 4
000000F8 E01FC080 DD PLL_BASE ; POOL-Entry U=1
000000FC E01FC000 DD MAM_BASE ; POOL-Entry U=1
00000100 40000490 DD Top_Stack ; POOL-Entry U=1
00000104 000002B9 DD ?C?INIT ; POOL-Entry U=1
00000108 000000F0 DD exit?A ; POOL-Entry U=1
0000010C 000000F5 DD exit?T ; POOL-Entry U=1
*** Disassembly of Segment '?PR?tc0?A?Intrp':
FILE: 'Intrp.c'
30: void tc0 (void) __irq {
00000128 tc0?A: ; FUNCTION START
00000128 E92D4703 STMDB R13!,{R0-R1,R8-R10,LR}
31: ++timeval;
0000012C E59F0060 MOV R0,[PC,+96] ; PoolRef @0x194 ; timeval
00000130 E5901000 LDR R1,[R0,#0x0] ; timeval
00000134 E2811001 ADD R1,R1,#0x0001
00000138 E5801000 STR R1,[R0,#0x0] ; timeval
32: if ((timeval % 10000) == 0) {
0000013C E59F0050 MOV R0,[PC,+80] ; PoolRef @0x194 ; timeval
00000140 E5900000 LDR R0,[R0,#0x0] ; timeval
00000144 E59F104C MOV R1,[PC,+76] ; PoolRef @0x198
00000148 EB00008C BL ?C?SDIV?A ; Targ=0x380 ; ?C?SDIV?A
0000014C E1A01000 MOV R1,R0
00000150 E3510000 CMP R1,#0x0000
00000154 1A000006 BNE L_1 ; Targ=0x174
33: timeval = 0;
00000158 E3A01000 MOV R1,#0x0
0000015C E59F0030 MOV R0,[PC,+48] ; PoolRef @0x194 ; timeval
00000160 E5801000 STR R1,[R0,#0x0] ; timeval
34: SecondCnt++;
00000164 E2800004 ADD R0,R0,#0x0004 ; timeval
00000168 E5901000 LDR R1,[R0,#0x0] ; SecondCnt
0000016C E2811001 ADD R1,R1,#0x0001
00000170 E5801000 STR R1,[R0,#0x0] ; SecondCnt
35: }
00000174 L_1:
36: T0IR = 1; // Clear interrupt flag
00000174 E3A01001 MOV R1,#0x1
00000178 E59F001C MOV R0,[PC,+28] ; PoolRef @0x19C
0000017C E5801000 STR R1,[R0,#0x0]
37: VICVectAddr = 0; // Acknowledge Interrupt
00000180 E3A01000 MOV R1,#0x0
00000184 E59F0014 MOV R0,[PC,+20] ; PoolRef @0x1A0
00000188 E5801000 STR R1,[R0,#0x0]
38: }
0000018C E8BD4703 LDMIA R13!,{R0-R1,R8-R10,LR}
00000190 E25EF004 SUBS R15,R14,#0x0004
00000194 ; END 'tc0?A'
00000194 40000494 DD timeval ; POOL-Entry U=3
00000198 00002710 DD 0x2710 ; POOL-Entry U=1
0000019C E0004000 DD 0xE0004000 ; POOL-Entry U=1
000001A0 FFFFF030 DD 0xFFFFF030 ; POOL-Entry U=1
*** Disassembly of Segment '?PR?init_timer?T?Intrp':
FILE: 'Intrp.c'
41: void init_timer (void) {
000001A4 init_timer?T: ; FUNCTION START
42: T0MR0 = 1499; // 0.1mSec = 1.500-1 counts
000001A4 4909 LDR R1,[R15,#36] ; PoolRef @0x1CC
000001A6 480A LDR R0,[R15,#40] ; PoolRef @0x1D0
000001A8 6001 STR R1,[R0,#0x0]
43: T0MCR = 3; // Interrupt and Reset on MR0
LA ARM LINKER/LOCATER V0.21 11/18/2004 14:06:02 PAGE 5
000001AA 2103 MOV R1,#0x3
000001AC 4809 LDR R0,[R15,#36] ; PoolRef @0x1D4
000001AE 6001 STR R1,[R0,#0x0]
44: T0TCR = 1; // Timer0 Enable
000001B0 2101 MOV R1,#0x1
000001B2 4809 LDR R0,[R15,#36] ; PoolRef @0x1D8
000001B4 6001 STR R1,[R0,#0x0]
45: VICVectAddr0 = (unsigned long)tc0; // set interrupt vector in 0
000001B6 4809 LDR R0,[R15,#36] ; PoolRef @0x1DC ; tc0?A
000001B8 1C01 MOV R1,R0 ; tc0?A
000001BA 4809 LDR R0,[R15,#36] ; PoolRef @0x1E0
000001BC 6001 STR R1,[R0,#0x0]
46: VICVectCntl0 = 0x20 | 4; // use it for Timer 0 Interrupt
000001BE 2124 MOV R1,#0x24
000001C0 4808 LDR R0,[R15,#32] ; PoolRef @0x1E4
000001C2 6001 STR R1,[R0,#0x0]
47: VICIntEnable = 0x00000010; // Enable Timer0 Interrupt
000001C4 2110 MOV R1,#0x10
000001C6 4808 LDR R0,[R15,#32] ; PoolRef @0x1E8
000001C8 6001 STR R1,[R0,#0x0]
48: }
000001CA 4770 BX R14
000001CC ; END 'init_timer?T'
000001CC 000005DB DD 0x5DB ; POOL-Entry U=1
000001D0 E0004018 DD 0xE0004018 ; POOL-Entry U=1
000001D4 E0004014 DD 0xE0004014 ; POOL-Entry U=1
000001D8 E0004004 DD 0xE0004004 ; POOL-Entry U=1
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