system_state.vhd

这是著名的硬件调试工具debussy的教学说明

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--   Debussy tutorial case: A simplified microprogramming-based CPU
--   file name: system.vhd
--   description: This file is used to initalize the target system
--                and set up the stimulus for the simulation

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
-- use work.my_pack.all;
entity system is
end system;

architecture Blk of system is

component CPU
port (clock : in std_logic;
 reset : in std_logic;
 VMA : out std_logic;
 R_W : out std_logic;
 addr : out std_logic_vector(7 downto 0);
 data : inout std_logic_vector(7 downto 0));
end component;

component pram2
port (clock : in std_logic;
 addr : in std_logic_vector(7 downto 0);
 VMA : in std_logic;
 R_W : in std_logic;
 dout : inout std_logic_vector(7 downto 0));
end component;

component fsm_master
port (Clock : in std_logic;
 Reset : in std_logic;
 ThreeOnly : in std_logic;
 FirstDataInRdy : in std_logic;
 StartFSM1 : out std_logic;
 StartFSM2 : out std_logic;
 StartFSM3 : out std_logic;
 FirstDataOutRdy : out std_logic);
end component;

component fsm_child1
port ( Clock : in std_logic;
 Reset : in std_logic;
 ThreeOnly : in std_logic;
 StartFSM1 : in std_logic;
 En_A, En_B, En_C, En_D : out std_logic);
end component;

component fsm_child2
port ( Clock : in std_logic;
 Reset : in std_logic;
 ThreeOnly : in std_logic;
 StartFSM2 : in std_logic;
 Mux1_Sel : out std_logic_vector(1 downto 0);
 Mux2_Sel : out std_logic_vector(1 downto 0);
 En_AB,En_AC,En_AD,En_BC,En_BD,En_CD : out std_logic);
end component;

component fsm_child3
port ( Clock : in std_logic;
 Reset : in std_logic;
 ThreeOnly : in std_logic;
 StartFSM3 : in std_logic;
 Mux3_Sel : out std_logic_vector(1 downto 0));
end component;


  signal clock    : std_logic ; -- :='0';
  signal reset    : std_logic ;
  signal data     : std_logic_vector(7 downto 0);
  signal VMA      : std_logic;
  signal R_W      : std_logic;
  signal addr     : std_logic_vector(7 downto 0);
  signal ctl_rst0 : std_logic :='0';
  signal ctl_rst1 : std_logic :='1';
  signal rst0     : std_logic :='0';
  signal rst1     : std_logic :='1';

  signal state_rst : std_logic := '0';
  signal ThreeOnly : std_logic := '0';
  signal FirstDataInRdy : std_logic := '0';
  signal En_A, En_B, En_C, En_D : std_logic;
  signal Mux1_Sel, Mux2_Sel : std_logic_vector( 1 downto 0);
  signal En_AB,En_AC,En_AD,En_BC,En_BD,En_CD : std_logic;
  signal Mux3_Sel : std_logic_vector( 1 downto 0);
  signal FirstDataOutRdy : std_logic;
  signal StartFSM1, StartFSM2, StartFSM3 : std_logic;

begin

 i_CPU: CPU
 port map ( clock => clock
        , reset => reset
        , VMA => VMA
        , R_W => R_W
        , data => data
        , addr => addr
        );

 i_pram: pram2
 port map ( clock => clock
        , addr => addr
        , VMA => VMA
        , R_W => R_W
        , dout => data
        );

 MASTER: fsm_master
 port map ( Clock => clock
	, Reset => state_rst
	, ThreeOnly => ThreeOnly
	, FirstDataInRdy => FirstDataInRdy
	, StartFSM1 => StartFSM1
	, StartFSM2 => StartFSM2
	, StartFSM3 => StartFSM3
	, FirstDataOutRdy => FirstDataOutRdy
	);

 CHILD1: fsm_child1
 port map ( Clock => clock
        , Reset => state_rst
        , ThreeOnly => ThreeOnly
	, StartFSM1 => StartFSM1
	, En_A => En_A
	, En_B => En_B
	, En_C => En_C
	, En_D => En_D
	);

 CHILD2: fsm_child2
 port map ( Clock => clock
        , Reset => state_rst
        , ThreeOnly => ThreeOnly
	, StartFSM2 => StartFSM2
	, Mux1_Sel => Mux1_Sel
	, Mux2_Sel => Mux2_Sel
	, En_AB => En_AB
	, En_AC => En_AC
	, En_AD => En_AD
	, En_BC => En_BC
	, En_BD => En_BD
	, En_CD => En_CD
	);

 CHILD3: fsm_child3
 port map ( Clock => clock
        , Reset => state_rst
        , ThreeOnly => ThreeOnly
	, StartFSM3 => StartFSM3
	, Mux3_Sel => Mux3_Sel
	);


 process
 begin
   wait for 25 ns;
   ctl_rst0 <='1';
   wait for 325 ns;
   ctl_rst0 <='0';
   wait ;
 end process;

 process
 begin
   wait for 50 ns;
   ctl_rst1 <= '0';
   wait for 300 ns;
   ctl_rst1 <='1';
   wait;
 end process;

 process (ctl_rst0)
 begin
    if(ctl_rst0 = '1') then
        reset <= rst0;
    else
	reset <= 'Z';
    end if;
 end process;

 process (ctl_rst1)
 begin
    if(ctl_rst1 = '1') then
        reset <= rst1;
    else
	reset <= 'Z';
    end if;
 end process;

 process
   variable flag : boolean := TRUE;
 begin
   wait for 250 ns;
   while flag loop
     clock <= '0';
     wait for 50 ns;
     clock <= '1';
     wait for 50 ns;
   end loop;
 end process;

 process
 begin
   wait for 500 ns;
     FirstDataInRdy <= '1';
 end process;


end Blk;