📄 1verilog.exm
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****************************** Figure 11.43 Simulation result
module test_events;
event EVENT;
initial begin // begin at time 0
$display ("begin at %d", $time);
@ EVENT;
$display ("EVENT at %d", $time);
end
initial begin // begin at time 0
#1;
->EVENT;
end
endmodule
****************************** Example 11.44 Time control and event
Highest level modules:
test_events
begin at 0
EVENT at 1
****************************** Figure 11.45 Simulation output
module flipflop_chain;
`define WIDTH 8
reg CP;
reg [`WIDTH-1:0] INPUT,
MIDDLE,
OUTPUT;
always @(posedge CP)
MIDDLE = #1 INPUT;
always @(posedge CP)
OUTPUT = #1 MIDDLE;
always @(INPUT or MIDDLE or OUTPUT)
$display ("time: %d, INPUT= %h MIDDLE= %h, OUTPUT= %h",
$time, INPUT, MIDDLE, OUTPUT);
always begin
CP = 0; #10;
CP = 1; #10;
end
initial begin
INPUT = 0; #20;
INPUT = 255; #20;
INPUT = 8'haa; #20;
$finish;
end
endmodule
Highest level modules:
flipflop_chain
time: 0, INPUT= 00 MIDDLE= xx, OUTPUT= xx
time: 11, INPUT= 00 MIDDLE= 00, OUTPUT= xx
time: 20, INPUT= ff MIDDLE= 00, OUTPUT= xx
time: 31, INPUT= ff MIDDLE= ff, OUTPUT= 00
time: 40, INPUT= aa MIDDLE= ff, OUTPUT= 00
time: 51, INPUT= aa MIDDLE= aa, OUTPUT= ff
L33 "bsp38.v": $finish at simulation time 60
****************************** Example 11.46 Flip-flop chain
module four_bit_adder (A4, B4, SUM5, NULL_FLAG);
input A4,
B4;
output SUM5,
NULL_FLAG;
wire [3:0] A4,
B4;
wire [4:0] SUM5;
wire [2:0] CARRY;
one_bit_adder Bit0 (A4[0], B4[0], 1'b0, SUM5[0], CARRY[0]);
one_bit_adder Bit1 (A4[1], B4[1], CARRY[0], SUM5[1], CARRY[1]);
one_bit_adder Bit2 (A4[2], B4[2], CARRY[1], SUM5[2], CARRY[2]);
one_bit_adder Bit3 (A4[3], B4[3], CARRY[2], SUM5[3], SUM5 [4]);
nor Nor_for_zeroflag
(NULL_FLAG, SUM5[0], SUM5[1], SUM5[2], SUM5[3], SUM5[4]);
endmodule
****************************** Example 11.47 Structure model of a 4-bit adder
module one_bit_adder (A, B, CARRY_IN, SUM, CARRY_OUT);
input A,
B,
CARRY_IN;
output SUM,
CARRY_OUT;
reg SUM,
CARRY_OUT;
always @(A or B or CARRY_IN)
{CARRY_OUT, SUM} = A + B + CARRY_IN;
endmodule
****************************** Example 11.48 Behavior model of a 1-bit adder
module four_bit_adder (A4, B4, SUM5, NULL_FLAG);
input A4,
B4;
output SUM5,
NULL_FLAG;
wire [3:0] A4,
B4;
reg NULL_FLAG;
reg [4:0] SUM5;
always @(A4 or B4) begin
SUM5 = A4 + B4;
NULL_FLAG = SUM5 == 0;
end
endmodule
****************************** Example 11.49 Behavior model of the 4-bit adder
module m (CLOCK, DATA); //00
input CLOCK; // local clock //01
inout [7:0] DATA; // bidirectional data port //02
//03
reg [7:0] BUFFER; // output driver //04
wire [7:0] DATA = BUFFER; // continuous assignment //05
reg [7:0] COUNTER; // counter //06
//07
parameter Start = 0; //08
//09
initial //10
COUNTER = Start; // initialization by parameter //11
//12
always @(posedge CLOCK) begin //13
BUFFER = COUNTER; // PRODUCER (write) //14
COUNTER = COUNTER + 1; //15
end //16
//17
always @(negedge CLOCK) //18
BUFFER = 8'bz; // PRODUCER (drive high impedance) //19
//20
always @(CLOCK or DATA) //21
if (Start == 0) //22
$display ("%3.0f %d %d", $time, CLOCK, DATA); //23
else //24
$display ("%3.0f %d %d", //25
$time, CLOCK, DATA); // CONSUMER (read and display) //26
endmodule // m //27
//28
//29
//30
module mainmodule; //31
wire [7:0] GLOBAL_DATA; // wire between instances //32
reg GLOBAL_CLOCK; // global clock //33
//34
defparam M1.Start = 0; // initialize counter of instances //35
defparam M2.Start = 100; // individually //36
//37
m M1 ( GLOBAL_CLOCK, GLOBAL_DATA); // instance M1 //38
m M2 (!GLOBAL_CLOCK, GLOBAL_DATA); // instance M2 with clock inverted //39
//40
initial begin // global clock //41
$display ("time M1.CLOCK M2.CLOCK M1.DATA M2.DATA"); //42
#10; //43
GLOBAL_CLOCK = 1; #10; GLOBAL_CLOCK = 0; #10; //44
GLOBAL_CLOCK = 1; #10; GLOBAL_CLOCK = 0; #10; //45
GLOBAL_CLOCK = 1; #10; GLOBAL_CLOCK = 0; #10; //46
end //47
endmodule // mainmodule //48
****************************** Example 11.51 Producer-consumer communication
Highest level modules:
mainmodule
time M1.CLOCK M2.CLOCK M1.DATA M2.DATA
10 0 x
10 1 x
10 0 0
10 1 0
20 1 0
20 0 0
20 0 100
20 1 100
30 0 100
30 1 100
30 0 1
30 1 1
40 1 1
40 0 1
40 0 101
40 1 101
50 0 101
50 1 101
50 0 2
50 1 2
60 1 2
60 0 2
60 0 102
60 1 102
209 simulation events
****************************** Figure 11.52 Simulation result
//-------------------------------------------------------------------- //00
// //01
// Model of one-phase pipeline //02
// //03
//-------------------------------------------------------------------- //04
//05
module pipeline; //06
//07
parameter High = 10, // clock high //08
Low = 5; // clock low //09
//10
reg CP; // clock //11
//12
reg [31:0] M1, S1, // master 1, slave 1 //13
M2, S2, // master 2, slave 2 //14
M3, S3, // master 3, slave 3 //15
M4, S4; // master 4, slave 4 //16
//17
integer i; // scratch //18
//19
//20
// Control pipeline and apply functions //21
always @(negedge CP) S1 = M1; //22
always @(posedge CP) M2 = f1(S1); always @(negedge CP) S2 = M2; //23
always @(posedge CP) M3 = f2(S2); always @(negedge CP) S3 = M3; //24
always @(posedge CP) M4 = f3(S3); always @(negedge CP) S4 = M4; //25
//26
// Logic between S1 and M2 //27
function [31:0] f1; //28
input [31:0] IN; //29
f1 = 2 * IN; //30
endfunction //31
//32
// Logic between S2 and M3 //33
function [31:0] f2; //34
input [31:0] IN; //35
f2 = IN + 5; //36
endfunction //37
//38
// Logic between S3 and M4 //39
function [31:0] f3; //40
input [31:0] IN; //41
f3 = IN * IN; //42
endfunction //43
//44
// One-phase clock //45
always begin //46
CP = 1; #High; // clock high //47
CP = 0; #Low; // clock low //48
end //49
//50
// Monitor of CP and all registers //51
always @(CP or M1 or S1 or M2 or S2 or M3 or S3 or M4 or S4) //52
begin //53
$write ("%5.0f %5.0f %3.0f %3.0f %3.0f %3.0f %3.0f ", //54
$time, CP, M1, S1, M2, S2, M3); //55
$display ("%3.0f %3.0f %3.0f", S3, M4, S4); //56
end //57
//58
// Output, test patterns //59
initial begin //60
$write (" Time CP M1 S1 M2 "); //61
$display (" S2 M3 S3 M4 S4 "); //62
//63
@(posedge CP) M1 = 1; // set M1 //64
@(posedge CP) M1 = 2; // set M1 //65
@(posedge CP) M1 = 3; // set M1 //66
@(posedge CP) M1 = 4; // set M1 //67
//68
for(i=1;i<=5;i=i+1) // clear pipeline //69
@(negedge CP); //70
$finish; //71
end //72
//73
endmodule // pipeline //74
Highest level modules:
pipeline
Time CP M1 S1 M2 S2 M3 S3 M4 S4
10 0 0 0 0 0 0 0 0 0
15 1 0 0 0 0 0 0 0 0
15 1 1 0 0 0 0 0 0 0
25 0 1 0 0 0 0 0 0 0
25 0 1 1 0 0 0 0 0 0
30 1 1 1 0 0 0 0 0 0
30 1 2 1 2 0 0 0 0 0
40 0 2 1 2 0 0 0 0 0
40 0 2 2 2 2 0 0 0 0
45 1 2 2 2 2 0 0 0 0
45 1 3 2 4 2 7 0 0 0
55 0 3 2 4 2 7 0 0 0
55 0 3 3 4 4 7 7 0 0
60 1 3 3 4 4 7 7 0 0
60 1 4 3 6 4 9 7 49 0
70 0 4 3 6 4 9 7 49 0
70 0 4 4 6 6 9 9 49 49
75 1 4 4 6 6 9 9 49 49
75 1 4 4 8 6 11 9 81 49
85 0 4 4 8 6 11 9 81 49
85 0 4 4 8 8 11 11 81 81
90 1 4 4 8 8 11 11 81 81
90 1 4 4 8 8 13 11 121 81
100 0 4 4 8 8 13 11 121 81
100 0 4 4 8 8 13 13 121 121
105 1 4 4 8 8 13 13 121 121
105 1 4 4 8 8 13 13 169 121
115 0 4 4 8 8 13 13 169 121
115 0 4 4 8 8 13 13 169 169
120 1 4 4 8 8 13 13 169 169
130 0 4 4 8 8 13 13 169 169
L72 "bsp101.v": $finish at simulation time 130
488 simulation events
****************************** Example 11.55 VERILOG model of the pipeline
//-------------------------------------------------------------------- //000
// //001
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