1verilog.exm

大型risc处理器设计源代码,这是书中的代码 基于流水线的risc cpu设计

always @(WIRE) begin
  $display ("time: %d, WIRE= %b", $time, WIRE);
  if (WIRE)
    $display ("if");
  else
    $display ("else");
  $display;
end

initial begin
  WIRE = 0;            #10;        // case 1
  WIRE = 1;            #10;        // case 2
  WIRE = 100;          #10;        // case 3
  WIRE = 8'b0000_001x; #10;        // case 4
  WIRE = 8'b1111_111z; #10;        // case 5
  WIRE = 8'bxxxx_xxxx; #10;        // case 6
  WIRE = 8'bzzzz_zzzz; #10;        // case 7
end
endmodule


Highest level modules:
if_test

time:                    0, WIRE= 00000000
else

time:                   10, WIRE= 00000001
if

time:                   20, WIRE= 01100100
if

time:                   30, WIRE= 0000001x
if

time:                   40, WIRE= 1111111z
if

time:                   50, WIRE= xxxxxxxx
else

time:                   60, WIRE= zzzzzzzz
else

****************************** Example 11.28   Alternatives

module selection;
reg  [1:0] ENABLE;
reg  [7:0] SOURCE,
           RESULT;

always @(ENABLE or SOURCE) begin
  RESULT = ENABLE ? SOURCE : 8'bxxxx_xxxx;
  $display ("time: %d, RESULT= %b", $time, RESULT);
end

initial begin
  SOURCE = 0;            #10;      // change of 8'bxxxx_xxxx to 0
  ENABLE = 1;            #10;      // change of 2'bxx to 2'b01
  SOURCE = 8'b0000_1010; #10;
  ENABLE = 2'b0x;        #10;
  ENABLE = 2'b0z;        #10;
  ENABLE = 2'b1x;        #10;
  $finish;
end
endmodule


Highest level modules:
selection

time:                    0, RESULT= xxxxxxxx
time:                   10, RESULT= 00000000
time:                   20, RESULT= 00001010
time:                   30, RESULT= xxxxxxxx
time:                   40, RESULT= xxxxxxxx
time:                   50, RESULT= 00001010
L18 "bsp26.v": $finish at simulation time 60

****************************** Example 11.29   Alternative with ?

module case_and_casez;
reg [1:0] SELECTION;

always @(SELECTION) begin
  $display ("time: %d, SELECTION= %b", $time, SELECTION);
  $display ("case:");
  case (SELECTION)
    2'b00:   $display ("2'b00");
    2'b01:   $display ("2'b01");
    2'b0x:   $display ("2'b0x");
    2'b0z:   $display ("2'b0z");
    default: $display ("undefined");
  endcase
  $display ("casez:");
  casez (SELECTION)
    2'b00:   $display ("2'b00");
    2'b01:   $display ("2'b01");
    2'b0x:   $display ("2'b0x");
    2'b0z:   $display ("2'b0z");
    default: $display ("undefined");
  endcase
  $display;
end

initial begin
  SELECTION = 2'b00; #10;
  SELECTION = 2'b0x; #10;
  SELECTION = 2'b0z; #10;
  SELECTION = 2'b??; #10;
end
endmodule


Highest level modules:
case_and_casez

time:                    0, SELECTION= 00
case:
2'b00
casez:
2'b00

time:                   10, SELECTION= 0x
case:
2'b0x
casez:
2'b0x

time:                   20, SELECTION= 0z
case:
2'b0z
casez:
2'b00

time:                   30, SELECTION= zz
case:
undefined
casez:
2'b00

****************************** Example 11.30   Case selection with case and casez

module while_loop;
reg [3:0] COUNTER;

initial begin
  COUNTER = 0;
  while (COUNTER <= 10) begin
    $display ("%d", COUNTER);
    COUNTER = COUNTER + 1;
  end
end
endmodule

****************************** Example 11.31   Loop with while

module forever_loop;
initial
  forever
    $display ("endless loop");

always
  $display ("endless loop");
endmodule

****************************** Example 11.32   Loop with forever

module for_loop;
reg [3:0] COUNTER;

initial
  for (COUNTER = 0; COUNTER <= 10; COUNTER = COUNTER + 1)
    $display ("%d", COUNTER);
endmodule

****************************** Example 11.33   Loop with for

module fork_join;

initial begin
  $display ("time: %d, begin", $time);
  fork
  begin                        // block 1
    $display ("B1 begin");
    #10;
    $display ("B1 end");
  end
  begin                        // block 2
    $display ("B2 begin");
    $display ("B2 end");
  end
  begin                        // block 3
    $display ("B3 begin");
    $display ("B3 end");
  end
  join
  $display ("time: %d, end", $time);
end
endmodule


Highest level modules:
fork_join

time:                    0, begin
B1 begin
B2 begin
B2 end
B3 begin
B3 end
B1 end
time:                   10, end

****************************** Example 11.34   Parallel fork-join

module module1;

`define TEXT "hello"
`define TIMES 3

reg [2:0] COUNTER;

initial
  for (COUNTER = 1; COUNTER <= `TIMES; COUNTER = COUNTER + 1)
    $display (`TEXT);
endmodule


module modul2;
reg [2:0] COUNTER;

initial
  for (COUNTER = 1; COUNTER <= `TIMES; COUNTER = COUNTER + 1)
    $display (`TEXT);
endmodule

****************************** Example 11.35   `define

module display_write;
reg [71:0] STRINGVARIABLE;
reg  [7:0] VARIABLE;

initial begin
  $display ("module name: %m");
  STRINGVARIABLE = "test";
  $display ("This is a %s", STRINGVARIABLE);
  VARIABLE = 100;
  $write ("100 decimal: %d, hexadecimal: %H\n ",
    VARIABLE, VARIABLE);
  $display ("octal: %O, binary: %b", VARIABLE, VARIABLE);
  $display ("binary without leading nulls: %0b", VARIABLE);
end
endmodule


Highest level modules:
display_write

module name: display_write
This is a      test
100 decimal: 100, hexadecimal: 64
octal: 144, binary: 01100100
binary without leading nulls: 1100100

****************************** Example 11.37   Output by $display and $write

module finish;
`define SIMULATIONTIME 4

always begin
  $display ("working");
  #1;
end

initial begin
  #`SIMULATIONTIME;
  $finish;
end
endmodule


Highest level modules:
finish

working
working
working
working

****************************** Example 11.38   End of simulation by $finish

module memory (S_ADDRESS, S_DATA);
input   [3:0] S_ADDRESS;                   // address
output  [7:0] S_DATA;                      // output
reg     [7:0] MEMORY [15:0];               // 16 8-bit words

assign        S_DATA = MEMORY [S_ADDRESS]; // continuous assignment

initial
  $readmemb ("memory_initial", MEMORY);    // initialize memory
endmodule

****************************** Example 11.39   Reading an array

// initial memory data
0000_0000 0000_0001 0000_0010 0000_0011
0000_0100 0000_0101 0000_0110 0000_0111
0000_1000 0000_1001 0000_1010 0000_1011
0000_1100 0000_1101 0000_1110 0000_1111

****************************** Example 11.40   Sample data



module event_control;

reg[4:0] N;

initial begin
  $display ("AAA");
  $display ("BBB");
end

initial
  for (N=0; N<=3; N=N+1)
    $display (N);

endmodule

****************************** Example 11.42   Parallelism and order of execution

Highest level modules:
event_control

AAA
BBB