1verilog.exm

大型risc处理器设计源代码,这是书中的代码 基于流水线的risc cpu设计

  $display ("1'bx  ==  1'b1  = %b", 1'bx  ==  1'b1);
  $display ("1'bx  === 1'b1  = %b", 1'bx  === 1'b1);
  $display ("1'bx  ==  1'bx  = %b", 1'bx  ==  1'bx);
  $display ("1'bx  === 1'bx  = %b", 1'bx  === 1'bx);
  $display ("1'bz  !=  1'b1  = %b", 1'bz  !=  1'b1);
  $display ("1'bx  <=  1'b1  = %b", 1'bx  <=  1'b1);
  $display ("2'bxx ==  2'b11 = %b", 2'bxx ==  2'b11);
end
endmodule


Highest level modules:
compare

1'bx  ==  1'b1  = x
1'bx  === 1'b1  = 0
1'bx  ==  1'bx  = x
1'bx  === 1'bx  = 1
1'bz  !=  1'b1  = x
1'bx  <=  1'b1  = x
2'bxx ==  2'b11 = x

****************************** Example 11.14   Compare operators

module logical_operators;

initial begin
  $display ("! 1'b1 = %b", ! 1'b1);
  $display ("! 1'bx = %b", ! 1'bx);
  $display ("! 1'bz = %b", ! 1'bz);
  $display ("1'b1  && 1'b0  = %b", 1'b1  && 1'b0 );
  $display ("1'bx  && 1'b0  = %b", 1'bx  && 1'b0 );
  $display ("1'bx  && 1'b1  = %b", 1'bx  && 1'b1 );
  $display ("1'bx  || 1'b0  = %b", 1'bx  || 1'b0 );
  $display ("1'bx  || 1'b1  = %b", 1'bx  || 1'b1 );
  $display ("2'b00 || 2'bxx = %b", 2'b00 || 2'bxx);
end
endmodule


Highest level modules:
logical_operators

! 1'b1 = 0
! 1'bx = x
! 1'bz = x
1'b1  && 1'b0  = 0
1'bx  && 1'b0  = 0
1'bx  && 1'b1  = x
1'bx  || 1'b0  = x
1'bx  || 1'b1  = 1
2'b00 || 2'bxx = x

****************************** Example 11.16   Logic operations

module bitwise_operators;

initial begin
  $display ("~ 4'bzx10         = %b", ~ 4'bzx10);
  $display ("4'b001x & 4'b0x10 = %b", 4'b001x & 4'b0x10);
  $display ("2'b1x | 2'b00     = %b", 2'b1x | 2'b00);
end
endmodule


Highest level modules:
bitwise_operators

~ 4'bzx10         = xx01
4'b001x & 4'b0x10 = 0010
2'b1x | 2'b00     = 1x

****************************** Example 11.17   Bit-wise operations

module concatenation;

initial
  $display ("{3'b100, 4'bxxzz, 2'ha} = %b", {3'b100, 4'bxxzz, 2'ha});
endmodule


Highest level modules:
concatenation

{3'b100, 4'bxxzz, 2'ha} = 100xxzz10

****************************** Example 11.18   Concatenation

module shift;

initial begin
  $display ("%b", 8'b0000_1111 << 4);
  $display ("%b", 8'b0000_1111 >> 4);
  $display ("%b", 8'b0000_1111 << -4);
end
endmodule


Highest level modules:
shift

11110000
00000000
00000000

****************************** Example 11.19   Shift

module trigger_event;
event EVENT;

always @ EVENT                    // wait for EVENT
  $display ("EVENT is triggered at time %d", $time);
                                  // $time is the simulation time

initial begin
  ->EVENT; #10;
  ->EVENT;                        // two events for the same
  ->EVENT; #10;                   // simulation time
  ->EVENT; #10;
  $finish;                        // end of simulation
end
endmodule


Highest level modules:
trigger_event

EVENT is triggered at time                    0
EVENT is triggered at time                   10
EVENT is triggered at time                   20
L16 "bsp18.v": $finish at simulation time 30

****************************** Example 11.20   Event triggering

module assign_test;
reg    REGISTER_VARIABLE;
wire   WIRE1 = REGISTER_VARIABLE;  // implicit continuous assignment
wire   WIRE2;
assign WIRE2 = REGISTER_VARIABLE;  // explicit continuous assignment

always @(WIRE1)
  $display ("time = %d: WIRE1 = %d", $time, WIRE1);

always @(WIRE2)
  $display ("time = %d: WIRE2 = %d", $time, WIRE2);

initial begin
  REGISTER_VARIABLE = 0; #10;
  REGISTER_VARIABLE = 1; #10;
  REGISTER_VARIABLE = 0;
  REGISTER_VARIABLE = 1; #10;
  $finish;
end
endmodule


Highest level modules:
assign_test

time =                    0: WIRE1 = 0
time =                    0: WIRE2 = 0
time =                   10: WIRE1 = 1
time =                   10: WIRE2 = 1
time =                   20: WIRE1 = 1
L21 "bsp19.v": $finish at simulation time 30

****************************** Example 11.21   Continuous assignment

module always_test;
reg [7:0] COUNTER;

always @(COUNTER)
  $display ("COUNTER has changed");

always @(COUNTER) begin
  $write ("time = %d    ", $time);
  $display ("COUNTER = %d", COUNTER);
end

always begin
  if (COUNTER === 8'bx)
    COUNTER = 0;                   // initialization
  else
    COUNTER = COUNTER + 1;
  if (COUNTER == 10)
    $finish;                       // finish simulation after 10 runs
  #10;                             // wait 10 time units
end

endmodule                                                               

Highest level modules:
always_test

time =                    0    COUNTER =   0
COUNTER has changed
COUNTER has changed
time =                   10    COUNTER =   1
time =                   20    COUNTER =   2
COUNTER has changed
COUNTER has changed
time =                   30    COUNTER =   3
time =                   40    COUNTER =   4
COUNTER has changed
COUNTER has changed
time =                   50    COUNTER =   5
time =                   60    COUNTER =   6
COUNTER has changed
COUNTER has changed
time =                   70    COUNTER =   7
time =                   80    COUNTER =   8
COUNTER has changed
COUNTER has changed
time =                   90    COUNTER =   9
L18 "bsp20.v": $finish at simulation time 100

****************************** Example 11.23   Parallel always blocks

module initial_test;
initial begin                      // initial block 1
  $display ("i1: a");
  $display ("i1: b");
  #10;
  $display ("i1: c");
end

initial begin                      // initial block 2
  $display ("i2: a");
  $display ("i2: b");
end
endmodule

****************************** Example 11.24   Parallel initial blocks

module events;
event EVENT1,
      EVENT2;
reg   CLOCK;

always @(posedge CLOCK)
  $display ("time: %d: rising  edge", $time);

always @(negedge CLOCK)
  $display ("time: %d: falling edge", $time);

always @(EVENT1 or EVENT2)
  $display ("time: %d: EVENT1 or EVENT2", $time);

initial begin
  CLOCK = 0; #10;
  CLOCK = 1; #10;
  CLOCK = 0; #10;
  ->EVENT1; #10;
  ->EVENT2; #10;
  $finish;
end
endmodule


Highest level modules:
events

time:                    0: falling edge
time:                   10: rising  edge
time:                   20: falling edge
time:                   30: EVENT1 or EVENT2
time:                   40: EVENT1 or EVENT2
L21 "bsp22.v": $finish at simulation time 50

****************************** Example 11.25   Event control @

module wait_test;
reg ENABLE;

always begin
  wait (ENABLE);
  $display ("time: %d", $time);
  #1;
end

always @(ENABLE)
  $display ("ENABLE= %d", ENABLE);

initial begin
  ENABLE = 1; #5;
  ENABLE = 0; #5;
  ENABLE = 1; #5;
  $finish;
end
endmodule


Highest level modules:
wait_test

ENABLE= 1
time:                    0
time:                    1
time:                    2
time:                    3
time:                    4
ENABLE= 0
ENABLE= 1
time:                   10
time:                   11
time:                   12
time:                   13
time:                   14
L17 "bsp23.v": $finish at simulation time 15

****************************** Example 11.26   wait

module time_delay;
reg WIRE;

always @(WIRE)
  $display ("time: %d, WIRE= %d", $time, WIRE);

initial begin
  WIRE = 0;
  #10;
  WIRE = #10 1;
  #10;
end
endmodule


Highest level modules:
time_delay

time:                    0, WIRE= 0
time:                   20, WIRE= 1

****************************** Example 11.27   Delay #

module if_test;
reg [7:0] WIRE;                    // 8 bit variable