1verilog.exm

大型risc处理器设计源代码,这是书中的代码 基于流水线的risc cpu设计

11   The Hardware Description Language VERILOG - Examples


module counter;
integer R;

initial
  for (R=1; R <= 10; R = R + 1)
    $display ("R= %d", R);
endmodule

****************************** Example 11.1   A module

module counter;
parameter Max = 0;

integer R;

initial
  for (R=1; R <= Max; R = R + 1)
    $display ("R= %d", R);
endmodule


module main_module;
defparam COUNTER1.Max   = 5,
         COUNTER2.Max   = 10;

counter COUNTER1 ();
counter COUNTER2 ();
endmodule

****************************** Example 11.2   Parameters

module begin_example;
reg A,
    B;

initial
  A = 1;

initial
  B = 1;

initial begin
  A = 1;
  B = 1;
end

initial begin : block1
  reg A_LOCAL;
  A_LOCAL = 1;
  B = A && A_LOCAL;
end
endmodule

****************************** Example 11.3   Compound statements

module task_example;
reg   [7:0] RESULT;

task add;
input [7:0] A,
            B;
RESULT = A + B;
endtask

task display_result;
$display ("The sum is %d", RESULT);
endtask

initial begin
  add (1, 2);
  display_result;
end
endmodule

****************************** Example 11.4   A task

module function_example;

function maximum;
input A,
      B;
if (A > B)
  maximum = A;
else
  maximum = B;
endfunction

initial begin
  $display ("maximum (0,0)=%d", maximum (0,0));
  $display ("maximum (1,0)=%d", maximum (1,0));
  $display ("maximum (0,1)=%d", maximum (0,1));
end
endmodule


VERILOG-XL 2.0.1   Jun  6, 1995  10:22:48

. . .

Compiling source file "bsp4.v"
Highest level modules:
function_example

maximum (0,0)=0
maximum (1,0)=1
maximum (0,1)=1
11 simulation events
CPU time: 0.5 secs to compile + 0.1 secs to link + 0.0 secs in simulation
End of VERILOG-XL 2.0.1   Jun  6, 1995  10:22:49

****************************** Example 11.5   Function with simulation output

module maximum (A, B, RESULT);
input  A,
       B;
output RESULT;
reg    RESULT;

always @(A or B)
  if (A > B)
    RESULT = A;
  else
    RESULT = B;
endmodule

****************************** Example 11.6   Module parameters

module submodule (VALUE, ENABLE);
inout [7:0] VALUE;
input       ENABLE;

reg   [7:0] BUFFER;
reg   [7:0] MEMORY;
wire  [7:0] VALUE = BUFFER;            // continuous assignment

always @(VALUE or ENABLE)
  if (ENABLE == 1) begin
    BUFFER = 8'bz;
    #2;
    MEMORY = VALUE;
  end
  else
    BUFFER = 255 - MEMORY;
endmodule


module mainmodul;
reg  [7:0] BUFFER;
wire [7:0] DATA = BUFFER;              // continuous assignment
reg        ENABLE;

submodule SUBMODULE (DATA, ENABLE);

initial begin
  BUFFER = 0;
  ENABLE = 1; #10;
  ENABLE = 0; #1;
  BUFFER = 8'bz;
  #10;
  $display ("DATA = %d", DATA);

  BUFFER = 100;
  ENABLE = 1; #10;
  ENABLE = 0; #1;
  BUFFER = 8'bz;
  #10;
  $display ("DATA = %d", DATA);
end
endmodule

****************************** Example 11.7   Bidirectional connection

module submodule1 (CLOCK_SUBMODULE1);
output CLOCK_SUBMODULE1;
reg    CLOCK_SUBMODULE1;

always begin
  CLOCK_SUBMODULE1 = 0;            // reset clock
  #10;                             // wait 10 time steps
  CLOCK_SUBMODULE1 = 1;            // set clock
  #10;                             // wait 10 time steps
end
endmodule


module submodule2 (CLOCK_SUBMODULE2, CLOCK_DIV_2_SUBMODULE2);
input  CLOCK_SUBMODULE2;
output CLOCK_DIV_2_SUBMODULE2;
reg    CLOCK_DIV_2_SUBMODULE2;

always begin
  CLOCK_DIV_2_SUBMODULE2 = 0;      // reset clock
  @(CLOCK_SUBMODULE2);             // wait twice
  @(CLOCK_SUBMODULE2);
  CLOCK_DIV_2_SUBMODULE2 = 1;      // set clock
  @(CLOCK_SUBMODULE2);             // wait twice
  @(CLOCK_SUBMODULE2);
end
endmodule


module mainmodule;
wire CLOCK_MAINMODULE,
     CLOCK_DIV_2_MAINMODULE;

submodule1 SUBMODULE1 (CLOCK_MAINMODULE);
submodule2 SUBMODULE2 (CLOCK_MAINMODULE, CLOCK_DIV_2_MAINMODULE);

always @(CLOCK_DIV_2_MAINMODULE)
  $display ("CLOCK_DIV_2_MAINMODULE changing");

initial begin
  #100;                            // wait 100 time steps
  $finish;                         // and finish simulation
end
endmodule

****************************** Example 11.8   Wires

module counter;
reg [3:0] R;

initial
  for (R=1; R <= 10; R = R + 1)
    $display ("R= %d", R);
endmodule

****************************** Example 11.9   Register

module send_receive;
reg [7:0] DATA;
event     STROBE;

// Sender
initial begin
  #10;
  DATA =   0; ->STROBE; #10;     // select DATA
  DATA = 100; ->STROBE; #10;     // trigger STROBE
  DATA = 255; ->STROBE; #10;     // and wait 10 steps
  DATA = 255; ->STROBE; #10;
end

// Receiver
always @ STROBE
  $display ("New value received is: %d", DATA);
endmodule

****************************** Example 11.10   Event

module send_receive_2;
reg [7:0] DATA;
reg       STROBE;

// Sender
initial begin
  #10;
  DATA =   0; STROBE = 1; #5; STROBE = 0; #5;   // select DATA,
  DATA = 100; STROBE = 1; #5; STROBE = 0; #5;   // STROBE pulse,
  DATA = 255; STROBE = 1; #5; STROBE = 0; #5;   // and wait
  DATA = 255; STROBE = 1; #5; STROBE = 0; #5;
end

// Receiver
always @(posedge STROBE)
  $display ("New value received is: %d", DATA);
endmodule

****************************** Example 11.11   Register instead of event

module constant_example;
reg  [7:0] DATA;

initial begin
  DATA =           0; $display ("DATA = %b", DATA);  // decimal   0
  DATA =          10; $display ("DATA = %b", DATA);  // decimal  10
  DATA =        'h10; $display ("DATA = %b", DATA);  // decimal  16
  DATA =        'b10; $display ("DATA = %b", DATA);  // decimal   2
  DATA =         255; $display ("DATA = %b", DATA);  // decimal 255
  DATA =        1'b1; $display ("DATA = %b", DATA);
  DATA =  'bxxxxzzzz; $display ("DATA = %b", DATA);
  DATA = 'b1010_1010; $display ("DATA = %b", DATA);
  DATA =        1'bz; $display ("DATA = %b", DATA);
  DATA =         'bz; $display ("DATA = %b", DATA);
end
endmodule


Highest level modules:
constant_example

DATA = 00000000
DATA = 00001010
DATA = 00010000
DATA = 00000010
DATA = 11111111
DATA = 00000001
DATA = xxxxzzzz
DATA = 10101010
DATA = 0000000z
DATA = zzzzzzzz

****************************** Example 11.12   Constants

module constant_example_2;
reg  [7:0] REG1,
           REG2;
wire [7:0] W = REG1;
assign     W = REG2;

initial begin
                                 $display ("W = %b", W);
  REG1 =  0; REG2 =           0; $display ("W = %b", W);
  REG1 = 10; REG2 =        8'bz; $display ("W = %b", W);
             REG2 = 8'b11111111; $display ("W = %b", W);
             REG2 =        8'bx; $display ("W = %b", W);
             REG2 =        8'bz; $display ("W = %b", W);
end
endmodule


Highest level modules:
constant_example_2

W = xxxxxxxx
W = 00000000
W = 00001010
W = xxxx1x1x
W = xxxxxxxx
W = 00001010

****************************** Example 11.13   x and z

module compare;

initial begin