2interpr.mod

大型risc处理器设计源代码,这是书中的代码 基于流水线的risc cpu设计

          end                                                                    i0596
        end                                                                      i0597
      `MISC_CLC: begin                                                           i0598
          if (~`KUMODE) SYSTEM_STATUS = `PRV_ERR;                                i0599
          LAST_CTR = 1'b0;                                                       i0600
        end                                                                      i0601
      `MISC_HALT: begin                                                          i0602
          if (`KUMODE) SYSTEM_STATUS = `STOPPED;                                 i0603
          else SYSTEM_STATUS = `PRV_ERR;                                         i0604
        end                                                                      i0605
      `MISC_LDH: begin                                                           i0606
          Write_Register(`IR_MISC_RD, {`IR_MISC_IMM, 13'b0}, `SWIACT);           i0607
          LAST_CTR = 1'b0;                                                       i0608
        end                                                                      i0609
      `MISC_BRANCH: Execute_Branch;                                              i0610
      default:      SYSTEM_STATUS = `INS_ERR;                                    i0611
    endcase                                                                      i0612
  end                                                                            i0613
  endtask                                                                        i0614
                                                                                 i0615
  //                                                                             i0616
  // Execute branch:                                                             i0617
  //   error state, if last instruction was CTR,                                 i0618
  //   otherwise,                                                                i0619
  //     set CTR status;                                                         i0620
  //     decide branch condition;                                                i0621
  //     get branch distance from instruction and extend with sign;              i0622
  //     if branch condition, put branch address into NPC,                       i0623
  //     otherwise, skip next instruction, if ANULL bit set                      i0624
  //                                                                             i0625
  task Execute_Branch;                                                           i0626
    reg [29:0] DISTANCE;                                                         i0627
    reg        DOBRANCH;                                                         i0628
  begin                                                                          i0629
    if (LAST_CTR) SYSTEM_STATUS = `CTR_ERR;                                      i0630
    else begin                                                                   i0631
        LAST_CTR = 1'b1;                                                         i0632
        case(`IR_MISC_BCC)                                                       i0633
          `MISC_BCC_GT: DOBRANCH = (~((`NFLAG ^ `VFLAG) |  `ZFLAG));             i0634
          `MISC_BCC_LE: DOBRANCH = ( ((`NFLAG ^ `VFLAG) |  `ZFLAG));             i0635
          `MISC_BCC_GE: DOBRANCH = ( ~(`NFLAG ^ `VFLAG) |  `ZFLAG);              i0636
          `MISC_BCC_LT: DOBRANCH = (  (`NFLAG ^ `VFLAG) & ~`ZFLAG);              i0637
          `MISC_BCC_HI: DOBRANCH =  (~(`CFLAG | `ZFLAG));                        i0638
          `MISC_BCC_LS: DOBRANCH =    (`CFLAG | `ZFLAG);                         i0639
          `MISC_BCC_PL: DOBRANCH =   (~`NFLAG);                                  i0640
          `MISC_BCC_MI: DOBRANCH =   ( `NFLAG);                                  i0641
          `MISC_BCC_NE: DOBRANCH =   (~`ZFLAG);                                  i0642
          `MISC_BCC_EQ: DOBRANCH =   ( `ZFLAG);                                  i0643
          `MISC_BCC_VC: DOBRANCH =   (~`VFLAG);                                  i0644
          `MISC_BCC_VS: DOBRANCH =   ( `VFLAG);                                  i0645
          `MISC_BCC_CC: DOBRANCH =   (~`CFLAG);                                  i0646
          `MISC_BCC_CS: DOBRANCH =   ( `CFLAG);                                  i0647
          `MISC_BCC_T:  DOBRANCH = `TRUE;                                        i0648
          `MISC_BCC_F:  DOBRANCH = `FALSE;                                       i0649
          default:      DOBRANCH = `FALSE;     // x or z                         i0650
        endcase                                                                  i0651
        DISTANCE[18: 0] = `IR_MISC_DISTANCE;   // compute branch distance        i0652
        DISTANCE[29:19] = {11{DISTANCE[18]}};                                    i0653
        if (DOBRANCH) NPC = LPC+DISTANCE;      // execute branch                 i0654
        if (!DOBRANCH && (`IR_MISC_ANULL == `MISC_ANULL)) begin                  i0655
          FPC = NPC;                           // annul delay slot               i0656
          NPC = NPC + 1;                                                         i0657
          LAST_CTR = 1'b0;                                                       i0658
        end                                                                      i0659
    end                                                                          i0660
  end                                                                            i0661
  endtask                                                                        i0662
                                                                                 i0663
  //                                                                             i0664
  // Execute CALL instruction:                                                   i0665
  //   error state, if last instruction was CTR,                                 i0666
  //   otherwise,                                                                i0667
  //     set CTR status;                                                         i0668
  //     save return address in Return-PC;                                       i0669
  //     transfer subroutine address in Next-PC                                  i0670
  //                                                                             i0671
  task Execute_CALL;                                                             i0672
  begin                                                                          i0673
    if (LAST_CTR) SYSTEM_STATUS = `CTR_ERR;                                      i0674
    else begin                                                                   i0675
           LAST_CTR = 1'b1;     // set CTR status                                i0676
           RPC = NPC;           // save return address                           i0677
           NPC = `IR_CALL_ADR;  // execute branch                                i0678
         end                                                                     i0679
  end                                                                            i0680
  endtask                                                                        i0681
                                                                                 i0682
  //                                                                             i0683
  // Read data from memory:                                                      i0684
  //   for a valid byte address, a word read access                              i0685
  //   is performed to the memory organized in words,                            i0686
  //   the read word data are filtered according to                              i0687
  //   data width and lower two byte address bits;                               i0688
  //   otherwise, read data are undefined ('x)                                   i0689
  //                                                                             i0690
  function [31:0] Read_Memory;                                                   i0691
    input [31:0] ADDR;                                                           i0692
    input [ 1:0] SIZE;                                                           i0693
    reg   [31:0] TEMP;                                                           i0694
  begin                                                                          i0695
    if (ADDR < `MEMSIZE) TEMP = MEMORY[ADDR >> 2];                               i0696
    else TEMP = {32{1'bx}};   // undefined outside memory                        i0697
    case(SIZE)                                                                   i0698
      `ACC_BYTE:  begin                  // read 8 bits                          i0699
          case(ADDR[1:0])                                                        i0700
            2'b00: Read_Memory = {24'b0, TEMP[ 7: 0]};                           i0701
            2'b01: Read_Memory = {24'b0, TEMP[15: 8]};                           i0702
            2'b10: Read_Memory = {24'b0, TEMP[23:16]};                           i0703
            2'b11: Read_Memory = {24'b0, TEMP[31:24]};                           i0704
          endcase                                                                i0705
        end                                                                      i0706
      `ACC_DBYTE: begin                  // read 16 bits                         i0707
          case(ADDR[1])                                                          i0708
            1'b0: Read_Memory = {16'b0, TEMP[15: 0]};                            i0709
            1'b1: Read_Memory = {16'b0, TEMP[31:16]};                            i0710
          endcase                                                                i0711
        end                                                                      i0712
      `ACC_QBYTE: Read_Memory = TEMP;    // read 32 bits                         i0713
    endcase                                                                      i0714
  end                                                                            i0715
  endfunction                                                                    i0716
                                                                                 i0717
  //                                                                             i0718
  // Write data into memory:                                                     i0719
  //   for a valid byte address,                                                 i0720
  //   the new memory word is determined                                         i0721
  //   according to data width and                                               i0722
  //   lower two byte address bits,                                              i0723
  //   and it is written into memory;                                            i0724
  //   otherwise, no memory access is performed                                  i0725
  //                                                                             i0726
  task Write_Memory;                                                             i0727
    input [31:0] ADDR;                                                           i0728
    input [31:0] DATA;                                                           i0729
    input [ 1:0] SIZE;                                                           i0730
    reg   [31:0] TEMP;                                                           i0731
  begin                                                                          i0732
    if (ADDR < `MEMSIZE) begin                                                   i0733
      TEMP = MEMORY[ADDR >> 2];                                                  i0734
      case(SIZE)                                                                 i0735
        `ACC_BYTE:  begin                  // write 8 bits                       i0736
            case(ADDR[1:0])                                                      i0737
              2'b00: TEMP[ 7: 0] = DATA[7:0];                                    i0738
              2'b01: TEMP[15: 8] = DATA[7:0];                                    i0739
              2'b10: TEMP[23:16] = DATA[7:0];                                    i0740
              2'b11: TEMP[31:24] = DATA[7:0];                                    i0741
            endcase                                                              i0742
          end                                                                    i0743
        `ACC_DBYTE: begin                  // write 16 bits