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RDAT[31:16] = {16{RDAT[15]}}; i0447
else RDAT[31:16] = 16'b0; i0448
end i0449
`MACC_ALIGN_Q: RDAT = Read_Memory(ADDR, `ACC_QBYTE); i0450
endcase i0451
Delayed_Write_Register(`IR_MACC_OPERAND, RDAT); i0452
PROTO_RACC = `TRUE; // note read access i0453
end i0454
`MACC_STORE: begin i0455
WDAT = Read_Register(`IR_MACC_OPERAND); i0456
casez(`IR_MACC_ALIGN) i0457
`MACC_ALIGN_B: Write_Memory(ADDR, WDAT, `ACC_BYTE); i0458
`MACC_ALIGN_D: Write_Memory(ADDR, WDAT, `ACC_DBYTE); i0459
`MACC_ALIGN_Q: Write_Memory(ADDR, WDAT, `ACC_QBYTE); i0460
endcase i0461
PROTO_WACC = `TRUE; // note write access i0462
end i0463
`MACC_SWAP: begin i0464
RDAT = Read_Memory(ADDR, `ACC_QBYTE); i0465
WDAT = Read_Register(`IR_MACC_OPERAND); i0466
Write_Memory(ADDR, WDAT, `ACC_QBYTE); i0467
Delayed_Write_Register(`IR_MACC_OPERAND, RDAT); i0468
PROTO_RACC = `TRUE; // note read access i0469
PROTO_WACC = `TRUE; // note write access i0470
PROTO_SIZE = `ACC_QBYTE; // note 32-bit access i0471
end i0472
endcase i0473
PROTO_ADDR = ADDR; // note write/read address i0474
PROTO_RDAT = RDAT; // note read data i0475
PROTO_WDAT = WDAT; // note write data i0476
LAST_CTR = 1'b0; // erase CTR status i0477
end i0478
endtask i0479
i0480
// i0481
// Execute miscellaneous instructions: i0482
// Return from interrupt (RETI): i0483
// error state, if last instruction was CTR i0484
// or if kernel mode not active, i0485
// otherwise, set CTR status, update Next-PC and i0486
// include return status in system status i0487
// (flags not delayed, KUMODE and SWIACT delayed); i0488
// Software interrupt (SWI): i0489
// error state, if last instruction was CTR, i0490
// otherwise, set CTR status, save return address and return status, i0491
// determine Next-PC from interrupt number and VBR and set status i0492
// delayed for kernel mode and software interrupt; i0493
// Load register from special register (LRFS): i0494
// select special register and write contents into destination register; i0495
// extend contents with null, if not 32 bits; i0496
// in user mode, only PC, RPC, LPC, and the lower four SR bits i0497
// can be read, otherwise error state; i0498
// Store register into special register (SRIS): i0499
// read word from register and i0500
// write relevant part into special register; i0501
// in user mode, only PC, RPC, LPC, and the lower four SR bits i0502
// can be written, otherwise error state; i0503
// SRIS PC is a CTR with respect to CTR status; i0504
// Clear cache (CLC): i0505
// no function in this model, i0506
// must not be used in user mode; i0507
// Halt: set system to state 'stopped'; i0508
// Load high (LDH): i0509
// get upper part of word as immediate from instruction, i0510
// fill up with nulls and write result into destination register; i0511
// Branch: call task Execute_Branch; i0512
// i0513
task Execute_MISC; i0514
reg [31:0] DATA; i0515
begin i0516
case (`IR_MISCOP) i0517
`MISC_RETI: begin // return from interrupt (CTR instruction) i0518
if (LAST_CTR) SYSTEM_STATUS = `CTR_ERR; i0519
else begin i0520
LAST_CTR = 1'b1; i0521
if (`KUMODE) begin i0522
NPC = SWI_RETURN; // return with delay slot i0523
STATUS[3:0] = SWI_STATUS[3:0]; // undelayed status i0524
DELAY_KUM1 = SWI_STATUS[7]; // KUMODE status (delayed) i0525
DELAY_SIA1 = SWI_STATUS[4]; // SWIACT status (delayed) i0526
end i0527
else SYSTEM_STATUS = `PRV_ERR; i0528
end i0529
end i0530
`MISC_SWI: begin // software interrupt (CTR instruction) i0531
if (LAST_CTR) SYSTEM_STATUS = `CTR_ERR; i0532
else begin i0533
LAST_CTR = 1'b1; i0534
if (~`SWIACT) begin i0535
SWI_RETURN = NPC; // save return address i0536
SWI_STATUS = STATUS; // save return status i0537
DELAY_KUM1 = 1'b1; // kernel status (delayed) i0538
DELAY_SIA1 = 1'b1; // SWI status (delayed) i0539
NPC = {VBR, 1'b1, `IR_MISC_SWICODE, 1'b0}; // "jump" i0540
end i0541
end i0542
end i0543
`MISC_LRFS: begin // load register from special register i0544
if (`KUMODE) i0545
case(`IR_MISC_RS1) // kernel accesses i0546
`MISC_PC: DATA = {FPC, 2'b0}; i0547
`MISC_RPC: DATA = {RPC, 2'b0}; i0548
`MISC_LPC: DATA = {LPC, 2'b0}; i0549
`MISC_SR: DATA = {24'b0, STATUS}; i0550
`MISC_VBR: DATA = {VBR, 8'b0}; i0551
`MISC_SISR: DATA = {24'b0, SWI_STATUS}; i0552
`MISC_SIRPC: DATA = {SWI_RETURN, 2'b0}; i0553
default: DATA = 32'bx; i0554
endcase i0555
else i0556
case(`IR_MISC_RS1) // user accesses i0557
`MISC_PC: DATA = {FPC, 2'b0}; i0558
`MISC_RPC: DATA = {RPC, 2'b0}; i0559
`MISC_LPC: DATA = {LPC, 2'b0}; i0560
`MISC_SR: DATA = {28'b0, STATUS[3:0]}; i0561
default: SYSTEM_STATUS = `PRV_ERR; i0562
endcase i0563
Write_Register(`IR_MISC_RD, DATA, `SWIACT); i0564
LAST_CTR = 1'b0; i0565
end i0566
`MISC_SRIS: begin // store register into special register i0567
if ((LAST_CTR) && (`IR_MISC_RD == `MISC_PC)) i0568
SYSTEM_STATUS = `CTR_ERR; i0569
else begin i0570
if (`IR_MISC_RD == `MISC_PC) LAST_CTR = 1'b1; i0571
else LAST_CTR = 1'b0; i0572
DATA = Read_Register(`IR_MISC_RS2); i0573
if (`KUMODE) i0574
case(`IR_MISC_RD) // kernel accesses i0575
`MISC_PC: NPC = DATA[31:2]; i0576
`MISC_RPC: RPC = DATA[31:2]; i0577
`MISC_LPC: LPC = DATA[31:2]; i0578
`MISC_SR: STATUS = DATA[ 7:0] & 8'b10011111; i0579
`MISC_VBR: VBR = DATA[31:8]; i0580
`MISC_SISR: SWI_STATUS = DATA[ 7:0] & 8'b10011111; i0581
`MISC_SIRPC: SWI_RETURN = DATA[31:2]; i0582
endcase i0583
else i0584
case(`IR_MISC_RD) // user accesses i0585
`MISC_PC: NPC = DATA[31:2]; i0586
`MISC_RPC: RPC = DATA[31:2]; i0587
`MISC_LPC: LPC = DATA[31:2]; i0588
`MISC_SR: STATUS = {STATUS[7:4], DATA[3:0]}; i0589
default: SYSTEM_STATUS = `PRV_ERR; i0590
endcase i0591
DELAY_KUM1 = `KUMODE; // load status delay pipeline, i0592
DELAY_KUM2 = `KUMODE; // as for SRIS SR (kernel mode), i0593
DELAY_SIA1 = `SWIACT; // changes have to occur without i0594
DELAY_SIA2 = `SWIACT; // delay i0595
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