📄 2interpr.mod
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`define NFLAG STATUS[3] // ALU.F result was negative i0149
`define ZFLAG STATUS[2] // ALU.F result was null i0150
`define VFLAG STATUS[1] // ALU.F operation was overflow i0151
`define CFLAG STATUS[0] // ALU.F operation was carry i0152
i0153
// Definitions for memory access width (read_memory, write_memory) i0154
`define ACC_BYTE 2'b00 i0155
`define ACC_DBYTE 2'b01 i0156
`define ACC_QBYTE 2'b10 i0157
i0158
// Definitions for system status codes i0159
`define STARTED 3'd0 // system started i0160
`define WORKING 3'd1 // system working i0161
`define STOPPED 3'd2 // system halted by instruction HALT i0162
`define CTR_ERR 3'd3 // system halt due to 'delayed CTR' i0163
`define PRV_ERR 3'd4 // system halt due to 'privilege violation' i0164
`define INS_ERR 3'd5 // system halt due to 'illegal instruction' i0165
i0166
// i0167
// Declaration of events and registers i0168
// i0169
i0170
// Event for processor initialization i0171
event reset; i0172
i0173
// Event for interpreter step i0174
event step_begin; i0175
i0176
// memory i0177
reg [31:0] MEMORY[0:(`MEMSIZE - 1) >> 2]; i0178
i0179
// Processor registers i0180
reg [31:0] REGFIL[0:35], // register file i0181
IR; // instruction register i0182
reg [29:0] LPC, // PC of instruction loaded (last) i0183
FPC, // PC of instruction to be loaded (fetch) i0184
NPC, // PC for program control (next fetch) i0185
RPC; // PC for return after CALL (return) i0186
reg [23:0] VBR; // vector base register i0187
reg [ 7:0] STATUS; // processor status register i0188
reg [29:0] SWI_RETURN; // SWI return address i0189
reg [ 7:0] SWI_STATUS; // SWI return status i0190
i0191
// Registers for status delay pipeline i0192
// (delay of KUMODE and SWIACT for SWI and RETI) i0193
reg DELAY_KUM1, // KUMODE with 1-step delay i0194
DELAY_KUM2, // KUMODE with 2-step delay i0195
DELAY_SIA1, // SWIACT with 1-step delay i0196
DELAY_SIA2; // SWIACT with 2-step delay i0197
i0198
// Registers of pipeline for write delay i0199
reg [ 4:0] DELAY_REG1, // register with 1-step delay i0200
DELAY_REG2; // register with 2-step delay i0201
reg [31:0] DELAY_DAT1, // data with 1-step delay i0202
DELAY_DAT2; // data with 2-step delay i0203
i0204
// Delay of SWIACT for write delay i0205
reg LAST_SWIACT; // SWI status in previous step (1-active) i0206
i0207
// Register for 'delayed CTR' condition i0208
reg LAST_CTR; // CTR status in previous step (1 if CTR) i0209
i0210
// System status register (internal to interpreter model only) i0211
reg[2:0] SYSTEM_STATUS; i0212
i0213
// Protocol of MACC memory accesses i0214
// for additional debugging i0215
reg[31:0] PROTO_ADDR, // memory address i0216
PROTO_RDAT, // read data i0217
PROTO_WDAT; // write data i0218
reg[ 2:0] PROTO_SIZE; // data access width i0219
reg PROTO_RACC, // 1: read data valid i0220
PROTO_WACC; // 1: write data valid i0221
i0222
i0223
// i0224
// Reset i0225
// i0226
always @reset i0227
RISC2_Reset; i0228
i0229
// i0230
// Processor step i0231
// i0232
always @step_begin i0233
RISC2_Step; i0234
i0235
// i0236
// Reset RISC2 system; i0237
// set Fetch-PC und Next-PC for start at address 0; i0238
// erase ALU switches; i0239
// deactivate software interrupt state; i0240
// initialize write pipeline i0241
// i0242
task RISC2_Reset; i0243
begin i0244
SYSTEM_STATUS = `STARTED; i0245
FPC = 0; // Fetch-PC i0246
NPC = FPC + 1; // Next-PC i0247
STATUS = 8'b10000000; // initialize status i0248
DELAY_REG1 = 0; // initialize register write delay i0249
DELAY_REG2 = 0; i0250
DELAY_KUM1 = 1'b1; // initialize status delay i0251
DELAY_KUM2 = 1'b1; i0252
DELAY_SIA1 = 1'b0; i0253
DELAY_SIA2 = 1'b0; i0254
LAST_SWIACT = 1'b0; // initialize SWIACT delay i0255
LAST_CTR = 1'b0; // initialize CTR register i0256
end i0257
endtask i0258
i0259
// i0260
// Execute one processor step: i0261
// set system into working state; i0262
// if in working state: i0263
// execute register write delay pipeline: i0264
// execute writing in 2-step delay stage; i0265
// shift from 1-step stage into 2-step stage; i0266
// set 1-step stage empty (R0 is read-only register); i0267
// execute status delay pipeline: i0268
// take KUMODE and SWIACT from 2-step delay stage; i0269
// shift from 1-step stage into 2-step stage; i0270
// set 1-step stage to valid status; i0271
// set data access protocol flags: no access; i0272
// fetch and execute new instruction i0273
// i0274
task RISC2_Step; i0275
begin i0276
if (SYSTEM_STATUS == `STARTED) i0277
SYSTEM_STATUS = `WORKING; // leave RESET state i0278
if (SYSTEM_STATUS == `WORKING) begin i0279
Write_Register(DELAY_REG2, DELAY_DAT2, LAST_SWIACT); i0280
DELAY_REG2 = DELAY_REG1; // FIFO pipeline for i0281
DELAY_DAT2 = DELAY_DAT1; // write delay i0282
DELAY_REG1 = 0; // of data registers i0283
LAST_SWIACT = `SWIACT; i0284
`KUMODE = DELAY_KUM2; // FIFO pipeline for i0285
`SWIACT = DELAY_SIA2; // delayed changes i0286
DELAY_KUM2 = DELAY_KUM1; // of status register i0287
DELAY_SIA2 = DELAY_SIA1; i0288
DELAY_KUM1 = `KUMODE; i0289
DELAY_SIA1 = `SWIACT; i0290
PROTO_RACC = `FALSE; // initialize protocol flags i0291
PROTO_WACC = `FALSE; // for memory accesses i0292
Fetch_Instruction; // fetch instruction i0293
Execute_Instruction; // execute instruction i0294
end i0295
end i0296
endtask i0297
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