2interpr.mod

大型risc处理器设计源代码,这是书中的代码 基于流水线的risc cpu设计

//----------------------------------------------------------------------------   i0000
//                                                                               i0001
// Interpreter Model                                                             i0002
//                                                                               i0003
// Instruction behavior of processor TOOBSIE                                     i0004
//                                                                               i0005
//----------------------------------------------------------------------------   i0006
                                                                                 i0007
//                                                                               i0008
// Changeable model data:                                                        i0009
//   Switches STEP, TRACE, MEMDUMP, REGDUMP, and ACCDUMP                         i0010
//   and memory dump limits MDUMPLO and MDUMPHI are implemented                  i0011
//   in the test module as parameters which are initialized here                 i0012
//   and which can be modified during simulation by                              i0013
//   RISC2_Test.<name> = <value>;.                                               i0014
//                                                                               i0015
`define STEP    0         // 0: no $stop, 1: $stop after every instruction       i0016
`define TRACE   0         // 0: dump after HALT, 1: dump after every instruction i0017
`define MEMDUMP 0         // 0: no memory dump, 1: memory dump                   i0018
`define REGDUMP 0         // 0: no register dump, 1: register dump               i0019
`define ACCDUMP 0         // 0: no access dump, 1: access dump                   i0020
`define MEMSIZE 'h001_000 // system memory size in bytes                         i0021
`define MDUMPLO 'h000_000 // first byte address for memory dump                  i0022
`define MDUMPHI 'h000_0FF // last byte address for memory dump                   i0023
`define PROGRAM "pgm.exe" // program file to be executed                         i0024
`define PRG_FORMAT 1      // program format: 0=binary, 1=hexadecimal             i0025
                                                                                 i0026
//                                                                               i0027
// General definitions                                                           i0028
//                                                                               i0029
`define    TRUE  1'b1                                                            i0030
`define    FALSE 1'b0                                                            i0031
                                                                                 i0032
module RISC2_System;                                                             i0033
                                                                                 i0034
  //                                                                             i0035
  // Definition of instruction groups                                            i0036
  //                                                                             i0037
  // This instruction group partitioning is for the behavior model only,         i0038
  // the first two opcode bits partition in four groups for a better readable    i0039
  // decoding.                                                                   i0040
  //                                                                             i0041
  // It is distinguished between the following four instruction groups:          i0042
  `define    IR_FORMAT        IR[31:30]  // instruction group                    i0043
  `define    FORMAT_ALU       2'b01      // ALU group                            i0044
  `define    FORMAT_MACC      2'b00      // memory access group                  i0045
  `define    FORMAT_MISC      2'b11      // miscellaneous group                  i0046
  `define    FORMAT_CALL      2'b10      // CALL instruction                     i0047
                                                                                 i0048
  // Definitions for ALU operations                                              i0049
  `define    IR_ALUOP         IR[29:26]  // ALU opcode field                     i0050
  `define    ALU_AND          4'b0000    // AND                                  i0051
  `define    ALU_OR           4'b0001    // OR                                   i0052
  `define    ALU_XOR          4'b0010    // XOR                                  i0053
  `define    ALU_LSL          4'b0100    // shift logical left                   i0054
  `define    ALU_LSR          4'b0101    // shift logical right                  i0055
  `define    ALU_ASR          4'b0110    // shift arithmetic right               i0056
  `define    ALU_ROT          4'b0111    // rotate right                         i0057
  `define    ALU_ADD          4'b1000    // add                                  i0058
  `define    ALU_ADDC         4'b1001    // add with carry                       i0059
  `define    ALU_SUB          4'b1010    // subtract                             i0060
  `define    ALU_SUBC         4'b1011    // subtract with carry                  i0061
  `define    ALU_MUL          4'b1110    // multiply                             i0062
  `define    ALU_DIV          4'b1111    // divide                               i0063
                                                                                 i0064
  // Definitions for ALU switches                                                i0065
  `define    ALUF_CSHF        4'b01??    // carry for LSL, LSR, ASR, and ROT     i0066
  `define    ALUF_CADD        4'b100?    // carry for ADD and ADDC               i0067
  `define    ALUF_CSUB        4'b101?    // carry for SUB and SUBC               i0068
  `define    ALUF_OVER        4'b10??    // overflow                             i0069
  `define    IR_ALUFLAGS      IR[25]     // F switch:                            i0070
  `define    ALUFLAGS_CALC    1'b1       //   switch                             i0071
  `define    IR_ALUS2_FORMAT  IR[24]     // O switch:                            i0072
  `define    ALUS2_IMM        1'b0       //   operand format immediate           i0073
  `define    IR_ALURD         IR[23:19]  // destination register                 i0074
  `define    IR_ALURS1        IR[18:14]  // operand register  (source1)          i0075
  `define    IR_ALUIS2        IR[13: 0]  // immediate operand (source2)          i0076
  `define    IR_ALURS2        IR[ 4: 0]  // operand register  (source2)          i0077
                                                                                 i0078
  // Definitions for memory access instructions Load, Store, and Swap            i0079
  `define    IR_MACCEP        IR[29:28]  // Load/Store opcode                    i0080
  `define    MACC_LOAD        2'b0?      // Load                                 i0081
  `define    MACC_STORE       2'b10      // Store                                i0082
  `define    MACC_SWAP        2'b11      // Swap                                 i0083
  `define    IR_MACC_SFLAG    IR[28]     // S switch: extend loaded data         i0084
  `define    MACC_SIGNED      1'b1       //            with sign                 i0085
  `define    IR_MACC_ALIGN    IR[27:25]  // access format:                       i0086
  `define    MACC_ALIGN_B     3'b0??     //   byte                               i0087
  `define    MACC_ALIGN_D     3'b1?0     //   halfword                           i0088
  `define    MACC_ALIGN_Q     3'b1?1     //   word                               i0089
  `define    IR_MACCS2_FORMAT IR[24]     // format of second source:             i0090
  `define    MACCS2_IMM       1'b0       //   immediate                          i0091
  `define    IR_MACC_OPERAND  IR[23:19]  // operand                              i0092
  `define    IR_MACC_RS1      IR[18:14]  // first source                         i0093
  `define    IR_MACC_IS2      IR[13: 0]  // second source immediate              i0094
  `define    IR_MACC_RS2      IR[ 4: 0]  // second source                        i0095
                                                                                 i0096
  // Definitions for miscellaneous instructions                                  i0097
  `define    IR_MISCOP        IR[29:24]  // MISC opcode                          i0098
  `define    MISC_BRANCH      6'b111100  // Branch                               i0099
  `define    MISC_RETI        6'b111110  // Return from interrupt                i0100
  `define    MISC_SWI         6'b111101  // Software interrupt                   i0101
  `define    MISC_HALT        6'b111111  // Halt                                 i0102
  `define    MISC_LDH         6'b100000  // Load high                            i0103
  `define    MISC_CLC         6'b100111  // Clear cache                          i0104
  `define    MISC_LRFS        6'b101010  // Load register from special register  i0105
  `define    MISC_SRIS        6'b101011  // Store register into special register i0106
  `define    IR_MISC_ANULL    IR[23]     // delay slot after branch:             i0107
  `define    MISC_ANULL       1'b1       //   annul                              i0108
  `define    IR_MISC_BCC      IR[22:19]  // branch condition:                    i0109
  `define    MISC_BCC_GT      4'b0110    //   greater than                       i0110
  `define    MISC_BCC_LE      4'b1110    //   less or equal                      i0111
  `define    MISC_BCC_GE      4'b0101    //   greater or equal                   i0112
  `define    MISC_BCC_LT      4'b1101    //   less than                          i0113
  `define    MISC_BCC_HI      4'b0011    //   higher than                        i0114
  `define    MISC_BCC_LS      4'b1011    //   less or equal                      i0115
  `define    MISC_BCC_PL      4'b0010    //   plus                               i0116
  `define    MISC_BCC_MI      4'b1010    //   minus                              i0117
  `define    MISC_BCC_NE      4'b0000    //   not equal                          i0118
  `define    MISC_BCC_EQ      4'b1000    //   equal                              i0119
  `define    MISC_BCC_VC      4'b0100    //   overflow clear                     i0120
  `define    MISC_BCC_VS      4'b1100    //   overflow set                       i0121
  `define    MISC_BCC_CC      4'b0001    //   carry clear                        i0122
  `define    MISC_BCC_CS      4'b1001    //   carry set                          i0123
  `define    MISC_BCC_T       4'b1111    //   always                             i0124
  `define    MISC_BCC_F       4'b0111    //   never                              i0125
  `define    IR_MISC_RD       IR[23:19]  // destination register (LDH/LRFS/SRIS) i0126
  `define    IR_MISC_DISTANCE IR[18: 0]  // branch distance                      i0127
  `define    IR_MISC_IMM      IR[18: 0]  // immediate value for LDH              i0128
  `define    IR_MISC_SWICODE  IR[ 3: 0]  // SWI interrupt number                 i0129
  `define    IR_MISC_RS1      IR[18:14]  // register for LRFS                    i0130
  `define    IR_MISC_RS2      IR[ 4: 0]  // register for SRIS                    i0131
                                                                                 i0132
  // Special register numbers                                                    i0133
  // for accesses by SRIS and LRFS                                               i0134
  `define    MISC_PC          4'b0000    // program counter                      i0135
  `define    MISC_RPC         4'b0001    // return PC                            i0136
  `define    MISC_LPC         4'b0010    // last PC                              i0137
  `define    MISC_SR          4'b0011    // status register                      i0138
  `define    MISC_VBR         4'b0101    // vector base register                 i0139
  `define    MISC_SISR        4'b1000    // SWI status register                  i0140
  `define    MISC_SIRPC       4'b1011    // SWI return PC                        i0141
                                                                                 i0142
  // Definitions for CALL                                                        i0143
  `define    IR_CALL_ADR      IR[29: 0]  // branch address                       i0144
                                                                                 i0145
  // Definitions for status register                                             i0146
  `define    KUMODE STATUS[7]          // status kernel(1)/user(0) mode          i0147
  `define    SWIACT STATUS[4]          // SWI status (1: active)                 i0148