📄 3_10serv
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CP_Cnt = CP_Cnt + 1; u0237
if (system.CHIP.IFU.KU_MODE) CP_Kernel_Cnt = CP_Kernel_Cnt + 1; u0238
if (system.CHIP.PCU.IF_HWIACT) CP_HWI_Cnt = CP_HWI_Cnt + 1; u0239
else begin u0240
if (system.CHIP.PCU.IF_EXCACT) CP_Except_Cnt = CP_Except_Cnt + 1; u0241
else if (system.CHIP.PCU.IF_SWIACT) CP_SWI_Cnt = CP_SWI_Cnt + 1; u0242
end u0243
if (!system.CHIP.STEP) begin u0244
CP_Wait_Cnt = CP_Wait_Cnt + 1; u0245
if (!LAST_WAIT) Wait_Cnt = Wait_Cnt + 1; u0246
end u0247
u0248
LAST_WAIT = !system.CHIP.STEP; u0249
u0250
// Count steps u0251
if (system.CHIP.IFU.SHIFT) begin u0252
Step_Cnt = Step_Cnt + 1; u0253
if (system.CHIP.IFU.KU_MODE) Step_Kernel_Cnt = Step_Kernel_Cnt + 1; u0254
if (system.CHIP.PCU.IF_HWIACT) Step_HWI_Cnt = Step_HWI_Cnt + 1; u0255
else begin u0256
if (system.CHIP.PCU.IF_EXCACT) u0257
Step_Except_Cnt = Step_Except_Cnt + 1; u0258
else if (system.CHIP.PCU.IF_SWIACT) Step_SWI_Cnt = Step_SWI_Cnt + 1; u0259
end u0260
end u0261
u0262
// Count IFU clocks u0263
if (system.CHIP.WORK_IF) IFU_Cnt = IFU_Cnt + 1; u0264
u0265
if (`TRACE) begin u0266
if (FIRST) begin u0267
FIRST = 1'b0; u0268
$display; u0269
$display("Trace: M = MPC hit"); u0270
$display(" B = BTC hit"); u0271
$display(" C = branch correction"); u0272
$display; u0273
$write(" clock # address "); u0274
$display("IF ID EX MA WB"); u0275
$write("------------------------"); u0276
$display("-----------------------------------------------"); u0277
end u0278
$display("%d %h %s %s %s %s %s %s %s %s %s %s %s %s", u0279
CP_Cnt, PC, u0280
M0, u0281
M1, system.CHIP.WORK_ID ? source(S1) : " ", u0282
M2, system.CHIP.WORK_EX ? source(S2) : " ", u0283
M3, system.CHIP.WORK_MA ? source(S3) : " ", u0284
M4, system.CHIP.WORK_WB ? source(S4) : " ", u0285
system.CHIP.IFU.MPC_HIT ? "M" : " ", u0286
system.CHIP.IFU.BTC_HIT ? "B" : " ", u0287
system.CHIP.IFU.BTC_CORRECT ? "C" : " "); u0288
end u0289
u0290
// u0291
// Statistical u0292
// evaluation u0293
// u0294
if (`STATISTICS) begin u0295
u0296
// Count instructions u0297
if (system.CHIP.WORK_FD & u0298
(system.CHIP.IFU.MPC_HIT | system.CHIP.IFU.BTC_HIT | u0299
system.CHIP.IFU.BTC_CORRECT | !system.CHIP.IFU.NO_ACC)) u0300
Ins_Cnt = Ins_Cnt + 1; u0301
if (system.CHIP.IFU.BTC_HIT & ~system.CHIP.IFU.BTC_CORRECT u0302
& system.CHIP.IFU.SHIFT) Ins_Cnt = Ins_Cnt + 1; u0303
u0304
// Count meaningful instructions u0305
if (system.CHIP.WORK_WB) begin u0306
Ins_Exec_Cnt = Ins_Exec_Cnt + 1; u0307
case(S4) u0308
2'b01: Ins_Exec_BTC = Ins_Exec_BTC + 1; u0309
2'b10: Ins_Exec_MPC = Ins_Exec_MPC + 1; u0310
2'b11: Ins_Exec_RAM = Ins_Exec_RAM + 1; u0311
endcase u0312
end u0313
u0314
if (system.CHIP.IFU.BTC_HIT & ~system.CHIP.IFU.BTC_CORRECT u0315
& system.CHIP.IFU.SHIFT) begin u0316
Ins_Exec_Cnt = Ins_Exec_Cnt + 1; u0317
Ins_Exec_BTC = Ins_Exec_BTC + 1; u0318
end u0319
u0320
if (system.CHIP.WORK_WB) Ins_Active_Cnt = Ins_Active_Cnt + 1; u0321
u0322
// Count operations u0323
if (system.CHIP.WORK_WB) u0324
if (I4 != 32'h49000000) Ops_Exec_Cnt = Ops_Exec_Cnt + 1; u0325
if (system.CHIP.IFU.BTC_HIT & ~system.CHIP.IFU.BTC_CORRECT u0326
& system.CHIP.IFU.SHIFT) Ops_Exec_Cnt = Ops_Exec_Cnt + 1; u0327
u0328
// Count instruction fetches u0329
if (system.CHIP.WORK_IF) begin u0330
if (~system.CHIP.IFU.NO_ACC&&(system.CHIP.IFU.CACHE_MODE[3:0]!=4'b0)) u0331
IF_Cnt = IF_Cnt + 1; u0332
if (~system.CHIP.IFU.NO_ACC&&(system.CHIP.IFU.CACHE_MODE[3:0]==4'b0)) u0333
IF_RAM_Cnt = IF_RAM_Cnt + 1; u0334
if (system.CHIP.IFU.NO_ACC&&(system.CHIP.IFU.CACHE_MODE[3:0]!=4'b0)) u0335
IF_Cache_Cnt = IF_Cache_Cnt + 1; u0336
end u0337
u0338
// Count MA accesses in parallel with cache accesses u0339
if (LAST_MA) begin u0340
if ((system.CHIP.IFU.BTC_HIT | system.CHIP.IFU.MPC_HIT) u0341
& system.CHIP.IFU.SHIFT) begin u0342
MA_Hit_Cnt = MA_Hit_Cnt + 1; u0343
if (~system.CHIP.IFU.BTC_CORRECT) begin u0344
MA_Hit_Exec_Cnt = MA_Hit_Exec_Cnt + 1; u0345
end u0346
Last_Miss = 1'b0; u0347
end u0348
else begin u0349
CP_Miss_Cnt = CP_Miss_Cnt + 1; u0350
if (!Last_Miss) begin u0351
MA_Miss_Cnt = MA_Miss_Cnt + 1; u0352
if (~system.CHIP.IFU.BTC_CORRECT) begin u0353
MA_Miss_Exec_Cnt = MA_Miss_Exec_Cnt + 1; u0354
end u0355
end u0356
Last_Miss = 1'b1; u0357
end u0358
end u0359
else Last_Miss = 1'b1; u0360
u0361
// BTC hits u0362
if (system.CHIP.IFU.BTC_HIT & system.CHIP.IFU.SHIFT) begin u0363
BTC_Cnt = BTC_Cnt + 1; u0364
if (~system.CHIP.IFU.BTC_CORRECT) begin u0365
BTC_Exec_Cnt = BTC_Exec_Cnt + 1; u0366
end u0367
end u0368
u0369
// MPC hits u0370
if (system.CHIP.IFU.MPC_HIT & system.CHIP.IFU.SHIFT) begin u0371
MPC_Cnt = MPC_Cnt + 1; u0372
if (~system.CHIP.IFU.BTC_CORRECT) begin u0373
MPC_Exec_Cnt = MPC_Exec_Cnt + 1; u0374
end u0375
end u0376
u0377
// u0378
// Branch decision forecast u0379
// u0380
// forecast, if CBra and flags invalid; u0381
// a CBra is a BCC but not BT or BF u0382
// u0383
if (system.CHIP.IFU.BTC_HIT // BTC hit u0384
& system.CHIP.IFU.SHIFT // end of step u0385
& ~system.CHIP.IFU.BTC_CORRECT // no branch correction u0386
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