📄 3_10serv
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reg last_direction_forward; // last branch of BTC was forward u0087
u0088
u0089
integer MNE_AND, MNE_AND_F, MNE_OR, MNE_OR_F, MNE_XOR, MNE_XOR_F, u0090
MNE_LSL, MNE_LSL_F, MNE_LSR, MNE_LSR_F, MNE_ASR, MNE_ASR_F, u0091
MNE_ROT, MNE_ROT_F, MNE_ADD, MNE_ADD_F, MNE_ADDC, MNE_ADDC_F, u0092
MNE_SUB, MNE_SUB_F, MNE_SUBC, MNE_SUBC_F, MNE_MUL, MNE_MUL_F, u0093
MNE_DIV, MNE_DIV_F, MNE_BGT, MNE_BGT_A, MNE_BLE, MNE_BLE_A, u0094
MNE_BGE, MNE_BGE_A, MNE_BLT, MNE_BLT_A, MNE_BHI, MNE_BHI_A, u0095
MNE_BLS, MNE_BLS_A, MNE_BPL, MNE_BPL_A, MNE_BMI, MNE_BMI_A, u0096
MNE_BNE, MNE_BNE_A, MNE_BEQ, MNE_BEQ_A, MNE_BVC, MNE_BVC_A, u0097
MNE_BVS, MNE_BVS_A, MNE_BCC, MNE_BCC_A, MNE_BCS, MNE_BCS_A, u0098
MNE_BT, MNE_BT_A, MNE_BF, MNE_BF_A, MNE_RETI, MNE_SWI, MNE_HALT, u0099
MNE_CALL, MNE_LDUB, MNE_LDUD, MNE_LDUQ, u0100
MNE_LDSB, MNE_LDSD, MNE_LDSQ, MNE_STB, MNE_STD, u0101
MNE_STQ, MNE_SWP, MNE_LDH, MNE_CLC, MNE_LRFS, MNE_SRIS, u0102
MNE_UNKNOWN; u0103
u0104
integer Ins_ALU, Ins_Flag, Ins_MA; u0105
u0106
integer i; u0107
u0108
u0109
// u0110
// Start if trace and u0111
// statistics are desired u0112
// u0113
initial if (`TRACE || `STATISTICS) fork u0114
u0115
begin // initialization u0116
// Set FIRST (output of header) u0117
FIRST = 1'b1; u0118
u0119
// Initialize counters u0120
CP_Cnt = 0; u0121
CP_Kernel_Cnt = 0; u0122
CP_Except_Cnt = 0; u0123
CP_SWI_Cnt = 0; u0124
CP_HWI_Cnt = 0; u0125
CP_Wait_Cnt = 0; u0126
Step_Cnt = 0; u0127
Step_Kernel_Cnt = 0; u0128
Step_Except_Cnt = 0; u0129
Step_SWI_Cnt = 0; u0130
Step_HWI_Cnt = 0; u0131
Wait_Cnt = 0; u0132
Ins_Cnt = 0; u0133
Ins_Exec_Cnt = 0; u0134
Ins_Exec_RAM = 0; u0135
Ins_Exec_MPC = 0; u0136
Ins_Exec_BTC = 0; u0137
Ins_Active_Cnt = 0; u0138
Ops_Exec_Cnt = 0; u0139
Bus_Cnt = 0; u0140
IF_Cnt = 0; u0141
IF_RAM_Cnt = 0; u0142
IF_Cache_Cnt = 0; u0143
BMA_Cnt = 0; u0144
MA_Cnt = 0; u0145
CP_Miss_Cnt = 0; u0146
MA_Miss_Cnt = 0; u0147
MA_Miss_Exec_Cnt = 0; u0148
MA_Hit_Cnt = 0; u0149
MA_Hit_Exec_Cnt = 0; u0150
BTC_Cnt = 0; u0151
BTC_Exec_Cnt = 0; u0152
MPC_Cnt = 0; u0153
MPC_Exec_Cnt = 0; u0154
BC_Cnt = 0; u0155
St_Cnt = 0; u0156
CBra_Pred = 0; u0157
Bcc_Width = 0; u0158
Bcc_Cnt = 0; u0159
CBra_Pred = 0; u0160
for (i=0; i<20; i=i+1) Bcc_Dist[i] = 0; u0161
MACC_Width = 0; u0162
for (i=0; i<17; i=i+1) MACC_Dist[i] = 0; u0163
MA_I_Cnt = 0; u0164
ALU_Width = 0; u0165
for (i=0; i<15; i=i+1) ALU_Imm[i] = 0; u0166
ALU_Cnt = 0; u0167
SRIS_Cnt = 0; u0168
NOP_Cnt = 0; u0169
IFU_Cnt = 0; u0170
Bcc_t_f = 0; u0171
Bcc_t_r = 0; u0172
Bcc_nt_f = 0; u0173
Bcc_nt_r = 0; u0174
LAST_WAIT = 1'b0; u0175
Last_Miss = 1'b0; u0176
MNE_AND = 0; MNE_AND_F = 0; MNE_OR = 0; MNE_OR_F = 0; MNE_XOR = 0; u0177
MNE_XOR_F = 0; MNE_LSL = 0; MNE_LSL_F = 0; MNE_LSR = 0; MNE_LSR_F = 0; u0178
MNE_ASR = 0; MNE_ASR_F = 0; MNE_ROT = 0; MNE_ROT_F = 0; MNE_ADD = 0; u0179
MNE_ADD_F = 0; MNE_ADDC = 0; MNE_ADDC_F = 0; MNE_SUB = 0; MNE_SUB_F = 0; u0180
MNE_SUBC = 0; MNE_SUBC_F = 0; MNE_MUL = 0; MNE_MUL_F = 0; MNE_DIV = 0; u0181
MNE_DIV_F = 0; MNE_BGT = 0; MNE_BGT_A = 0; MNE_BLE = 0; MNE_BLE_A = 0; u0182
MNE_BGE = 0; MNE_BGE_A = 0; MNE_BLT = 0; MNE_BLT_A = 0; MNE_BHI = 0; u0183
MNE_BHI_A = 0; MNE_BLS = 0; MNE_BLS_A = 0; MNE_BPL = 0; MNE_BPL_A = 0; u0184
MNE_BMI = 0; MNE_BMI_A = 0; MNE_BNE = 0; MNE_BNE_A = 0; MNE_BEQ = 0; u0185
MNE_BEQ_A = 0; MNE_BVC = 0; MNE_BVC_A = 0; MNE_BVS = 0; MNE_BVS_A = 0; u0186
MNE_BCC = 0; MNE_BCC_A = 0; MNE_BCS = 0; MNE_BCS_A = 0; MNE_BT = 0; u0187
MNE_BT_A = 0; MNE_BF = 0; MNE_BF_A = 0; MNE_RETI = 0; MNE_SWI = 0; u0188
MNE_HALT = 0; MNE_CALL = 0; MNE_LDUB = 0; MNE_LDUD = 0; u0189
MNE_LDUQ = 0; MNE_LDSB = 0; MNE_LDSD = 0; MNE_LDSQ = 0; u0190
MNE_STB = 0; MNE_STD = 0; MNE_STQ = 0; MNE_SWP = 0; u0191
MNE_LDH = 0; MNE_CLC = 0; MNE_LRFS = 0; MNE_SRIS = 0; MNE_UNKNOWN = 0; u0192
Ins_ALU = 0; u0193
Ins_Flag = 0; u0194
Ins_MA = 0; u0195
H2 = 0; H3 = 0; H4 = 0; u0196
S1 = 0; S2 = 0; S3 = 0; S4 = 0; u0197
end u0198
u0199
// u0200
// Instruction pipeline u0201
// u0202
forever @(posedge system.CP) if (system.CHIP.nRESET && !H4) begin u0203
if (system.CHIP.WORK_WB) I4 = I3; u0204
if (system.CHIP.WORK_MA) I3 = I2; u0205
if (system.CHIP.WORK_EX) I2 = I1; u0206
if (system.CHIP.WORK_ID) I1 = system.CHIP.I_BUS; u0207
u0208
if (system.CHIP.WORK_WB) S4 = S3; u0209
if (system.CHIP.WORK_MA) S3 = S2; u0210
if (system.CHIP.WORK_EX) S2 = S1; u0211
if (system.CHIP.WORK_ID) S1 = u0212
(system.CHIP.IFU.BTC_HIT & ~system.CHIP.IFU.BTC_CORRECT u0213
& system.CHIP.IFU.SHIFT) ? 2'b01 : u0214
((system.CHIP.IFU.MPC_HIT & system.CHIP.IFU.SHIFT) ? 2'b10 : u0215
(system.CHIP.IFU.SHIFT ? 2'b11 : 2'b00)); u0216
u0217
PC = {system.CHIP.IFU.NEW_PC, 2'b0}; u0218
M0 = system.CHIP.IFU.BTC_HIT & ~system.CHIP.IFU.BTC_CORRECT ? u0219
(system.CHIP.IFU.BTC_TYPE ? " CALL" : " BCC") : "*****"; u0220
M1 = system.CHIP.WORK_ID ? mnemonic(I1) : "*****"; u0221
M2 = system.CHIP.WORK_EX ? mnemonic(I2) : "*****"; u0222
M3 = system.CHIP.WORK_MA ? mnemonic(I3) : "*****"; u0223
M4 = system.CHIP.WORK_WB ? mnemonic(I4) : "*****"; u0224
u0225
// Pipeline for signal TAKEN u0226
if (system.CHIP.WORK_WB) T4 = T3; u0227
if (system.CHIP.WORK_MA) T3 = T2; u0228
if (system.CHIP.WORK_EX) T2 = system.CHIP.IFU.TAKEN; u0229
u0230
// Pipeline for signal HALT u0231
if (system.CHIP.WORK_WB) H4 = H3; u0232
if (system.CHIP.WORK_MA) H3 = H2; u0233
if (system.CHIP.WORK_EX) H2 = system.CHIP.DO_HALT; u0234
u0235
// Count clocks u0236
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