📄 3_10serv
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//---------------------------------------------------------------------------- t0000
// t0001
// TEST t0002
// t0003
// Control file for simulation t0004
// t0005
//---------------------------------------------------------------------------- t0006
t0007
`define TRACE 1 // instructions t0008
`define STATISTICS 0 // statistics at the end t0009
`define DUMP 0 // hex-dump t0010
`define STEP 0 // dump in single step mode t0011
`define EXTRACE 0 // dump after every instruction t0012
`define MEMDUMP 1 // system memory dump t0013
`define REGDUMP 0 // register dump t0014
`define BTCDUMP 0 // BTC dump t0015
`define MPCDUMP 0 // MPC dump t0016
`define MDUMPLO 'h0000 // memory dump: first address t0017
`define MDUMPHI 'h00ff // memory dump: last address t0018
`define WAVES 0 // graphwaves t0019
`define REGS 0 // not supported t0020
t0021
// System t0022
`define PROTOCOL 0 // bus protocol: 1=synchronous, 0=asynchronoust0023
`define QUAD_CYCLE 25 // clock period / 4 t0024
`define RESET_TIME 525 // reset pulse length t0025
`define MAX_CYCLES 500000 // maximum number of clock cycles t0026
`define MHS_TIME 80 // MHS pulse length without wait states t0027
`define PROGRAM "example.exe" // RAM: initial file t0028
`define OS_ROM "vos.exe" // operating system ROM: initial file t0029
`define PRG_FORMAT 1 // format of user program: 0=binary, 1=hext0030
`define OS_FORMAT 1 // format of operating system: 0=binary, 1=hext0031
`define USER_RAM_SIZE 13 // number of word address bits (13=32KB) t0032
`define KERNEL_RAM_SIZE 13 // number of word address bits (13=32KB) t0033
`define ROM_SIZE 10 // number of word address bits (10= 4KB) t0034
`define RAMTIME 60 // RAM access time t0035
`define ROMTIME 60 // ROM access time t0036
`define WAITSTATE 8'b00000000 // wait states for memory accesses t0037
`define PAGEFAULTS 0 // page fault requests: 0=no, 1=yes t0038
`define DMAILEAVE 0 // DMA interleave: 0=no, 1=yes t0039
`define CHK_EN 1 // checking: 0=off, 1=on t0040
`define CHK_STP_EN 1 // stop, if checking error: 0=off, 1=on t0041
`define CHK_HGH_BITs 1 // check high bits (ADDR[29:..]): 0=off, 1=on t0042
// <=> RAM not "cyclic" t0043
t0044
// Cache mode t0045
`define SERIAL_MODE 1'b0 // 0=parallel mode, 1=serial mode t0046
`define EN_MEM_BRK 1'b1 // MEMBRK for asynchronous bus protocol t0047
`define IC_MODE 1'b1 // instruction cache mode: 0=off, 1=on t0048
`define RIB_MODE 1'b0 // reduced instruction buffer mode: 0=off, 1=on t0049
`define BTC_CALL 1'b1 // store CALLs in BTC t0050
`define BTC_BCC 1'b1 // store BCCs in BTC t0051
t0052
// Register transfer delay in simulation time units t0053
`define DELTA 1 t0054
t0055
// Delay for nMRQ after rising clock edge (> DELTA) t0056
`define BCUDELAY 2 t0057
//---------------------------------------------------------------------------- u0000
// u0001
// TRACE: evaluation and statistics u0002
// u0003
//---------------------------------------------------------------------------- u0004
u0005
module trace; u0006
reg [31:0] I1, // instruction code of ID u0007
I2, // instruction code of EX u0008
I3, // instruction code of MA u0009
I4; // instruction code of WB u0010
reg [31:0] PC; // program counter u0011
reg [5*8:1] M0, // mnemonic of IF u0012
M1, // mnemonic of ID u0013
M2, // mnemonic of EX u0014
M3, // mnemonic of MA u0015
M4; // mnemonic of WB u0016
reg T2, // taken flag of EX u0017
T3, // taken flag of MA u0018
T4; // taken flag of WB u0019
reg H2, // halt in EX u0020
H3, // halt in MA u0021
H4; // halt in WB u0022
reg [1:0] S1, // source of instruction in ID u0023
S2, // source of instruction in EX u0024
S3, // source of instruction in MA u0025
S4; // source of instruction in EX u0026
integer CP_Cnt, // # clocks u0027
CP_Kernel_Cnt, // # clocks in kernel mode u0028
CP_Except_Cnt, // # clocks in exception u0029
CP_SWI_Cnt, // # clocks in SWI u0030
CP_HWI_Cnt, // # clocks in HWI u0031
CP_Wait_Cnt, // # wait clocks (HALT, MHS) u0032
Step_Cnt, // # steps u0033
Step_Kernel_Cnt, // # steps in kernel mode u0034
Step_Except_Cnt, // # steps in exception u0035
Step_SWI_Cnt, // # steps in SWI u0036
Step_HWI_Cnt, // # steps in HWI u0037
Wait_Cnt, // # steps with waits u0038
Ins_Cnt, // # instructions total u0039
Ins_Exec_Cnt, // # executed instructions u0040
Ins_Exec_RAM, // # meaningful instructions from RAM u0041
Ins_Exec_MPC, // # meaningful instructions from MPC u0042
Ins_Exec_BTC, // # meaningful instructions from BTC u0043
Ins_Active_Cnt, // # instructions in WB u0044
Ops_Exec_Cnt, // # executed operations u0045
Bus_Cnt, // # bus accesses u0046
IF_Cnt, // # fetch accesses (RAM and cache) u0047
IF_RAM_Cnt, // # fetch accesses (RAM) u0048
IF_Cache_Cnt, // # fetch accesses (cache) u0049
BMA_Cnt, // # fetch aborts u0050
MA_Cnt, // # data accesses u0051
CP_Miss_Cnt, // # clocks with miss and data access u0052
MA_Miss_Cnt, // # cache misses during data accesses u0053
MA_Hit_Cnt, // # cache hits during data accesses u0054
MA_Miss_Exec_Cnt, // # misses of meaningful instructions u0055
MA_Hit_Exec_Cnt, // # hits of meaningful instructions u0056
BTC_Cnt, // # BTC hits u0057
BTC_Exec_Cnt, // # BTC hits, meaningful u0058
MPC_Cnt, // # MPC hits u0059
MPC_Exec_Cnt, // # MPC hits, meaningful u0060
St_Cnt, // # ST.* u0061
BC_Cnt, // # branch corrections u0062
CBra_Pred, // # heuristic branch decisions u0063
Bcc_Width, // bit length of branch distance u0064
Bcc_Dist[19:0], // branch distance distribution u0065
Bcc_Cnt, // # BCCs u0066
MACC_Width, // bit length of immediate MACC operandu0067
MACC_Dist[16:0], // immediate width distribution u0068
MA_I_Cnt, // # immediate MACCs u0069
ALU_Width, // bit length of immediate ALU operand u0070
ALU_Imm[14:0], // immediate width distribution u0071
ALU_Cnt, // # ALU operations u0072
SRIS_Cnt, // # SRIS PC u0073
NOP_Cnt, // # NOPs u0074
IFU_Cnt, // # clocks with WORK_IF u0075
Bcc_t_f, // # branches taken, forward u0076
Bcc_t_r, // # branches taken, backwards u0077
Bcc_nt_f, // # branches not taken, forward u0078
Bcc_nt_r; // # branches not taken, backwards u0079
reg LAST_WAIT; // processor did wait u0080
reg LAST_MA; // MA had bus access u0081
reg Last_Miss; // cache miss in last step u0082
reg FIRST; // header output u0083
reg [18:0] Dist; // branch distance distribution u0084
reg [13:0] Dist_MACC; // MACC immediate width distribution u0085
reg [13:0] Dist_ALU; // ALU immediate width distribution u0086
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