📄 3_07pcu
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end f0596
f0597
// f0598
// Hardware interrupt state for IF f0599
// f0600
always @(posedge CP) begin f0601
if (STEP) begin f0602
casez({DO_HWI, KILL_ALU, DO_RETI, ID_HWIACT, ID_EXCACT, ID_SWIACT, f0603
SRIS_KSR}) f0604
7'b1??????: NEXT_HWIACT = #`DELTA 1'b1; // HWI f0605
7'b0011???: NEXT_HWIACT = #`DELTA HWISR[6]; // HWI RETI f0606
7'b00101??: NEXT_HWIACT = #`DELTA EXCSR[6]; // EXC RETI f0607
7'b001001?: NEXT_HWIACT = #`DELTA SWISR[6]; // SWI RETI f0608
7'b000???1: NEXT_HWIACT = #`DELTA B_BUS[6]; // SRIS SR f0609
endcase f0610
end f0611
end f0612
f0613
// f0614
// Exception state for IF f0615
// f0616
always @(posedge CP) begin f0617
if (STEP) begin f0618
casez({KILL_ALU, DO_EXC, DO_RETI, ID_HWIACT, ID_EXCACT, ID_SWIACT, f0619
SRIS_KSR}) f0620
7'b01?????: NEXT_EXCACT = #`DELTA 1'b1; // exception f0621
7'b0011???: NEXT_EXCACT = #`DELTA HWISR[5]; // HWI RETI f0622
7'b00101??: NEXT_EXCACT = #`DELTA EXCSR[5]; // EXC RETI f0623
7'b001001?: NEXT_EXCACT = #`DELTA SWISR[5]; // SWI RETI f0624
7'b000???1: NEXT_EXCACT = #`DELTA B_BUS[5]; // SRIS SR f0625
endcase f0626
end f0627
end f0628
f0629
// f0630
// Software interrupt state for IF f0631
// f0632
always @(posedge CP) begin f0633
if (STEP) begin f0634
casez({KILL_ALU, DO_SWI, DO_RETI, ID_HWIACT, ID_EXCACT, ID_SWIACT, f0635
SRIS_KSR}) f0636
7'b01?????: NEXT_SWIACT = #`DELTA 1'b1; // SWI f0637
7'b0011???: NEXT_SWIACT = #`DELTA HWISR[4]; // HWI RETI f0638
7'b00101??: NEXT_SWIACT = #`DELTA EXCSR[4]; // EXC RETI f0639
7'b001001?: NEXT_SWIACT = #`DELTA SWISR[4]; // SWI RETI f0640
7'b000???1: NEXT_SWIACT = #`DELTA B_BUS[4]; // SRIS SR f0641
endcase f0642
end f0643
end f0644
f0645
//-------------------------------------------------------------------------- f0646
// f0647
// Status pipeline: IF stage f0648
// f0649
// Handling of IF status bits for f0650
// KUMODE, HWI, exception, and SWI f0651
// f0652
//-------------------------------------------------------------------------- f0653
f0654
// f0655
// Kernel/user mode for this IF step f0656
// f0657
always @(posedge CP) begin f0658
if (STEP) begin f0659
casez({DO_HWI, DO_PANIC, KILL_ALU, DO_EXC, DO_SWI, DO_RETI, ID_HWIACT, f0660
ID_EXCACT, ID_SWIACT, SRIS_KSR, (~DIS_IDU | EMERG_FETCH)}) f0661
11'b1?????????1: IF_KUMODE = #`DELTA 1'b1; // HWI f0662
11'b01????????1: IF_KUMODE = #`DELTA 1'b1; // PANIC f0663
11'b0001??????1: IF_KUMODE = #`DELTA 1'b1; // exception f0664
11'b00001?????1: IF_KUMODE = #`DELTA 1'b1; // SWI f0665
11'b0000011???1: IF_KUMODE = #`DELTA HWISR[7]; // HWI RETI f0666
11'b00000101??1: IF_KUMODE = #`DELTA EXCSR[7]; // EXC RETI f0667
11'b000001001?1: IF_KUMODE = #`DELTA SWISR[7]; // SWI RETI f0668
11'b000000???1?: IF_KUMODE = #`DELTA B_BUS[7]; // SRIS SR f0669
11'b?????????00: IF_KUMODE = #`DELTA IF_KUMODE; // hold state f0670
default: IF_KUMODE = #`DELTA NEXT_KUMODE; f0671
endcase f0672
end f0673
end f0674
f0675
// f0676
// Hardware interrupt state for this IF step f0677
// f0678
always @(posedge CP) begin f0679
if (STEP) begin f0680
casez({DO_HWI, KILL_ALU, DO_RETI, ID_HWIACT, ID_EXCACT, ID_SWIACT, f0681
SRIS_KSR, (~DIS_IDU | EMERG_FETCH)}) f0682
8'b1??????1: IF_HWIACT = #`DELTA 1'b1; // HWI f0683
8'b0011???1: IF_HWIACT = #`DELTA HWISR[6]; // HWI RETI f0684
8'b00101??1: IF_HWIACT = #`DELTA EXCSR[6]; // EXC RETI f0685
8'b001001?1: IF_HWIACT = #`DELTA SWISR[6]; // SWI RETI f0686
8'b000???1?: IF_HWIACT = #`DELTA B_BUS[6]; // SRIS SR f0687
8'b??????00: IF_HWIACT = #`DELTA IF_HWIACT; // hold state f0688
default: IF_HWIACT = #`DELTA NEXT_HWIACT; f0689
endcase f0690
end f0691
end f0692
f0693
// f0694
// Exception state for this IF step f0695
// f0696
always @(posedge CP) begin f0697
if (STEP) begin f0698
casez({KILL_ALU, DO_EXC, DO_RETI, ID_HWIACT, ID_EXCACT, ID_SWIACT, f0699
SRIS_KSR, (~DIS_IDU | EMERG_FETCH)}) f0700
8'b01?????1: IF_EXCACT = #`DELTA 1'b1; // exception f0701
8'b0011???1: IF_EXCACT = #`DELTA HWISR[5]; // HWI RETI f0702
8'b00101??1: IF_EXCACT = #`DELTA EXCSR[5]; // EXC RETI f0703
8'b001001?1: IF_EXCACT = #`DELTA SWISR[5]; // SWI RETI f0704
8'b000???1?: IF_EXCACT = #`DELTA B_BUS[5]; // SRIS SR f0705
8'b??????00: IF_EXCACT = #`DELTA IF_EXCACT; // hold state f0706
default: IF_EXCACT = #`DELTA NEXT_EXCACT; f0707
endcase f0708
end f0709
end f0710
f0711
// f0712
// Software interrupt state for this IF step f0713
// f0714
always @(posedge CP) begin f0715
if (STEP) begin f0716
casez({KILL_ALU, DO_SWI, DO_RETI, ID_HWIACT, ID_EXCACT, ID_SWIACT, f0717
SRIS_KSR, (~DIS_IDU | EMERG_FETCH)}) f0718
8'b01?????1: IF_SWIACT = #`DELTA 1'b1; // SWI f0719
8'b0011???1: IF_SWIACT = #`DELTA HWISR[4]; // HWI RETI f0720
8'b00101??1: IF_SWIACT = #`DELTA EXCSR[4]; // EXC RETI f0721
8'b001001?1: IF_SWIACT = #`DELTA SWISR[4]; // SWI RETI f0722
8'b000???1?: IF_SWIACT = #`DELTA B_BUS[4]; // SRIS SR f0723
8'b??????00: IF_SWIACT = #`DELTA IF_SWIACT; // hold state f0724
default: IF_SWIACT = #`DELTA NEXT_SWIACT; f0725
endcase f0726
end f0727
end f0728
f0729
//-------------------------------------------------------------------------- f0730
// f0731
// Status pipeline: ID stage f0732
// f0733
// Save delay slot status of ID instruction; f0734
// save program counter of ID instruction; f0735
// handling of ID status bits f0736
// f0737
//-------------------------------------------------------------------------- f0738
f0739
// f0740
// Save delay slot status of present instruction f0741
// f0742
always @(posedge CP) f0743
if (STEP) DS_IN_IDU = #`DELTA DS_IN_IFU; ⌨️ 快捷键说明
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