📄 3_07pcu
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// f0447
// PC_BUS to IFU f0448
// f0449
always @(DO_STARTUP or DO_HWI or DO_PANIC or DO_EXC or DO_SWI or f0450
KILL_ALU or DO_RETI or ID_HWIACT or ID_EXCACT or ID_SWIACT or f0451
SREG_ACC_DIR or SREG_ADDR or RERUN_MA or DS_IN_MAU or f0452
VBR or IRQ_IDREG or EXCEPT_ID or SWI_ID or f0453
HWIRPC or EXCRPC or SWIRPC or B_BUS or PC_MA or PC_WB) f0454
begin f0455
casez({DO_STARTUP, DO_HWI, DO_PANIC, KILL_ALU, DO_EXC, DO_SWI, DO_RETI, f0456
ID_HWIACT, ID_EXCACT, ID_SWIACT, SREG_ACC_DIR, SREG_ADDR, f0457
RERUN_MA, DS_IN_MAU}) f0458
17'b1????????????????: PC_BUS = 30'b0; // start f0459
17'b01???????????????: PC_BUS = {VBR, 2'b00, IRQ_IDREG, 1'b0}; // HWI f0460
17'b001??????????????: PC_BUS = {VBR, 2'b01, 3'b111, 1'b0}; // PANIC f0461
17'b00001????????????: PC_BUS = {VBR, 2'b01, EXCEPT_ID, 1'b0}; // EXC f0462
17'b000001???????????: PC_BUS = {VBR, 1'b1, SWI_ID, 1'b0}; // SWI f0463
17'b00000011???????0?: PC_BUS = HWIRPC; // HWI RETI f0464
17'b00000011???????10: PC_BUS = PC_MA; // HWI RETI f0465
17'b00000011???????11: PC_BUS = PC_WB; // HWI RETI f0466
17'b000000101????????: PC_BUS = EXCRPC; // EXC RETI f0467
17'b0000001001???????: PC_BUS = SWIRPC; // SWI RETI f0468
17'b0000000???10000??: PC_BUS = B_BUS[31:2]; // SRIS PC f0469
endcase f0470
end f0471
f0472
//-------------------------------------------------------------------------- f0473
// f0474
// BCU logic f0475
// f0476
// Access mode, access direction, and access privilege f0477
// for memory accesses by the BCU f0478
// f0479
//-------------------------------------------------------------------------- f0480
f0481
// f0482
// BCU_ACC_MODE f0483
// (access unit and width) f0484
// f0485
always @(WORK_MA or MAU_OPCODE3 or MAU_ACC_MODE3) begin f0486
casez({WORK_MA, MAU_OPCODE3, MAU_ACC_MODE3}) f0487
7'b100?0??: BCU_ACC_MODE = 3'b000; // MAU load (BYTE) f0488
7'b100?1?0: BCU_ACC_MODE = 3'b001; // MAU load (DBYTE) f0489
7'b100?1?1: BCU_ACC_MODE = 3'b010; // MAU load (QBYTE) f0490
7'b10100??: BCU_ACC_MODE = 3'b000; // MAU store (BYTE) f0491
7'b10101?0: BCU_ACC_MODE = 3'b001; // MAU store (DBYTE) f0492
7'b10101?1: BCU_ACC_MODE = 3'b010; // MAU store (QBYTE) f0493
7'b1011???: BCU_ACC_MODE = 3'b010; // MAU swap (QBYTE) f0494
default: BCU_ACC_MODE = 3'b110; // IFU fetch (QBYTE) f0495
endcase f0496
end f0497
f0498
// f0499
// BCU_ACC_DIR (access direction) f0500
// f0501
always @(WORK_MA or MAU_OPCODE3) begin f0502
casez({WORK_MA, MAU_OPCODE3}) f0503
4'b1010: BCU_ACC_DIR = 2'b01; // MAU store f0504
4'b1011: BCU_ACC_DIR = 2'b10; // MAU swap f0505
default: BCU_ACC_DIR = 2'b00; // MAU load and IFU fetch f0506
endcase f0507
end f0508
f0509
// f0510
// SYS_KUMODE (access privilege) f0511
// f0512
always @(MAU_USES_BUS or IF_KUMODE or MA_STATUS) begin f0513
casez(MAU_USES_BUS) f0514
1'b0: SYS_KUMODE = IF_KUMODE; // IFU bus access f0515
1'b1: SYS_KUMODE = MA_STATUS[7]; // MAU bus access f0516
endcase f0517
end f0518
f0519
//-------------------------------------------------------------------------- f0520
// f0521
// Status forwarding logic f0522
// f0523
// Instructions of type ALU.F and SRIS SR f0524
// determine flags for the next step; f0525
// these are required in this step, because f0526
// - a branch decision depends on them f0527
// - a hardware interrupt must save these flags f0528
// f0529
//-------------------------------------------------------------------------- f0530
f0531
// f0532
// Flags for IF branch decision f0533
// f0534
always @(SRIS_SR or NEW_FLAGS_DEL or FLAGS_FROM_ALU or FLAGS or B_BUS) f0535
begin f0536
casez({SRIS_SR, NEW_FLAGS_DEL}) f0537
2'b00: IF_FLAGS = FLAGS; // status register flags f0538
2'b1?: IF_FLAGS = B_BUS[3:0]; // SRIS SR f0539
2'b01: IF_FLAGS = FLAGS_FROM_ALU; // .F instruction f0540
endcase f0541
end f0542
f0543
// f0544
// Flags for FD branch decision f0545
// f0546
always @(NEW_FLAGS_DEL or FLAGS_FROM_ALU or FLAGS) f0547
begin f0548
casez(NEW_FLAGS_DEL) f0549
1'b0: FD_FLAGS = FLAGS; // status register flags f0550
1'b1: FD_FLAGS = FLAGS_FROM_ALU; // .F instruction f0551
endcase f0552
end f0553
f0554
// f0555
// Mode for present IF step; f0556
// consideration of instruction SRIS SR f0557
// in ID stage with kernel privilege f0558
// f0559
always @(SRIS_KSR or B_BUS or f0560
IF_KUMODE or IF_HWIACT or IF_EXCACT or IF_SWIACT) f0561
begin f0562
case(SRIS_KSR) f0563
1'b0: IF_MODE = {IF_KUMODE, IF_HWIACT, IF_EXCACT, IF_SWIACT}; f0564
1'b1: IF_MODE = B_BUS[7:4]; f0565
endcase f0566
end f0567
f0568
//-------------------------------------------------------------------------- f0569
// f0570
// Status pipeline: PF stage f0571
// f0572
// After completion of fetch, f0573
// handling of IF status bits for f0574
// KUMODE, HWI, exception, and SWI f0575
// f0576
//-------------------------------------------------------------------------- f0577
f0578
// f0579
// Kernel/user mode for IF f0580
// f0581
always @(posedge CP) begin f0582
if (STEP) begin f0583
casez({DO_HWI, DO_PANIC, KILL_ALU, DO_EXC, DO_SWI, DO_RETI, f0584
ID_HWIACT, ID_EXCACT, ID_SWIACT, SRIS_KSR}) f0585
10'b1?????????: NEXT_KUMODE = #`DELTA 1'b1; // HWI f0586
10'b01????????: NEXT_KUMODE = #`DELTA 1'b1; // PANIC f0587
10'b0001??????: NEXT_KUMODE = #`DELTA 1'b1; // exception f0588
10'b00001?????: NEXT_KUMODE = #`DELTA 1'b1; // SWI f0589
10'b0000011???: NEXT_KUMODE = #`DELTA HWISR[7]; // HWI RETI f0590
10'b00000101??: NEXT_KUMODE = #`DELTA EXCSR[7]; // EXC RETI f0591
10'b000001001?: NEXT_KUMODE = #`DELTA SWISR[7]; // SWI RETI f0592
10'b000000???1: NEXT_KUMODE = #`DELTA B_BUS[7]; // SRIS SR f0593
endcase f0594
end f0595
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