📄 3_07pcu
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wire [31:0] MAU_ADDR_BUS; // MAU memory access address f0149
wire [31:2] IFU_ADDR_BUS, // fetch PC from IFU (memory access address) f0150
NPC; // next PC from IFU (return PC for CALL and SWI)f0151
wire [ 3:0] SREG_ADDR; // special register address from IDU f0152
wire [ 2:0] MAU_ACC_MODE2, // access width and mode for MA from IDU f0153
MAU_OPCODE2; // opcode for MA f0154
wire CP, // processor clock f0155
nRESET, // reset f0156
nIRQ, // system interrupt request f0157
BCU_READY, // no memory access in progress f0158
CALL_NOW, // CALL instruction in ID f0159
IFU_CORRECT, // IFU corrects branch decision f0160
DS_IN_IFU, // CTR in ID and delay instruction in IF f0161
DIS_IDU, // disable IDU f0162
DIS_ALU, // disable ALU f0163
SREG_ACC_DIR, // access direction for special register f0164
SWI_RQ, // IDU requests SWI f0165
EXCEPT_RQ, // IDU requests exception f0166
DO_HALT, // IDU decoded HALT f0167
DO_RETI, // IDU decoded RETI f0168
NEW_FLAGS; // flag changing ALU instruction in ID (.F) f0169
f0170
// Registers for internal use f0171
reg [31:0] HWIADR, // address when HWI f0172
EXCADR; // address requesting exception f0173
reg [31:2] RPC, // return PC f0174
HWIRPC, // interrupt return PC for HWI f0175
EXCRPC, // IRPC for exceptions f0176
SWIRPC, // IRPC for software interrupts f0177
PC_ID, // PC of instruction in ID f0178
PC_EX, // PC of instruction in EX f0179
PC_MA, // PC of instruction in MA f0180
PC_WB; // PC of instruction in WB f0181
reg [31:8] VBR; // vector base register f0182
reg [ 7:0] EX_STATUS, // SR of instruction in EX f0183
MA_STATUS, // SR of instruction in MA f0184
SWISR, // SR for RETI after SWI f0185
EXCSR, // SR for RETI after EXC f0186
HWISR; // SR for RETI after HWI f0187
reg [ 3:0] IF_MODE, // IF mode (when SRIS SR in IDU) f0188
FLAGS, // present flags f0189
IF_FLAGS, // flags for IF branch decision f0190
FD_FLAGS; // flags for FD branch decision f0191
reg [ 2:0] IRQ_IDREG; // hardware interrupt code f0192
reg IRQ_REG, // hardware interrupt request f0193
DS_IN_IDU, // BCC/CALL in EX and delay instruction in IDU f0194
DS_IN_ALU, // BCC/CALL in MA and delay instruction in ALU f0195
DS_IN_MAU, // BCC/CALL in WB and delay instruction in MAU f0196
MAU_USES_BUS, // MAU uses processor bus f0197
NEW_FLAGS_DEL, // flag changing ALU instruction in EX f0198
NEXT_KUMODE, // kernel/user mode after fetch f0199
NEXT_HWIACT, // hardware interrupt state after fetch f0200
NEXT_SWIACT, // software interrupt state after fetch f0201
NEXT_EXCACT, // exception state after fetch f0202
IF_HWIACT, // hardware interrupt state for IF f0203
IF_SWIACT, // software interrupt state for IF f0204
IF_EXCACT, // exception state for IF f0205
ID_HWIACT, // hardware interrupt state for ID f0206
ID_SWIACT, // software interrupt state for ID f0207
ID_EXCACT, // exception state for ID f0208
DO_HWI, // hardware interrupt request f0209
DO_EXC, // exception request f0210
DO_SWI, // software interrupt request f0211
DO_PANIC, // interrupt routine error f0212
DO_STARTUP, // fill pipeline (after RESET) f0213
FLUSH_PIPE, // flush pipeline (when MAU HWI) f0214
RERUN_MA, // rerun at MA (MAU HWI when IFU HWI) f0215
PANIC, // interrupt error in progress f0216
SRIS_SR, // valid SRIS SR f0217
SRIS_KSR, // valid kernel SRIS SR f0218
SRIS_HISR, // valid SRIS HISR f0219
SRIS_HIRPC; // valid SRIS HIRPC f0220
f0221
f0222
// f0223
// Assignments for outputs f0224
// f0225
// Select interrupt overlay register set depending on interrupt f0226
wire [ 1:0] INT_STATE = {ID_HWIACT, (ID_EXCACT | ID_SWIACT)}; f0227
f0228
// New STEP when memory access completed f0229
wire STEP = BCU_READY; f0230
f0231
// Turn off IDU f0232
wire KILL_IDU = DIS_IDU | EMERG_FETCH; f0233
f0234
// MAU accesses memory f0235
wire LDST_ACC_NOW = (~MAU_OPCODE3[2] & ~RERUN_MA); f0236
f0237
// Carry flag f0238
wire ALU_CARRY = FD_FLAGS[0]; f0239
f0240
f0241
// f0242
// Assignments for internal use f0243
// f0244
wire [31:2] PC_IF = IFU_ADDR_BUS; // PC of instruction in IF f0245
f0246
// IF status f0247
wire [7:0] IF_STATUS = {IF_MODE, IF_FLAGS}; f0248
f0249
// ID status f0250
wire [7:0] ID_STATUS = {ID_KUMODE, ID_HWIACT, ID_EXCACT, ID_SWIACT, FD_FLAGS}; f0251
f0252
// Turn off ALU f0253
wire KILL_ALU = DIS_ALU | FLUSH_PIPE | (IFU_CORRECT & DO_HWI); f0254
f0255
f0256
// f0257
// Instance f0258
// f0259
f0260
work_unit WORK_UNIT ( f0261
WORK_IF, WORK_FD, WORK_ID, WORK_EX, WORK_MA, WORK_WB, f0262
CP, nRESET, STEP, DIS_IDU, KILL_ALU, RERUN_MA, f0263
FLUSH_PIPE, EMERG_FETCH, DO_HALT f0264
); f0265
f0266
//-------------------------------------------------------------------------- f0267
// f0268
// RESET logic f0269
// f0270
// Asynchronous initialization of all registers f0271
// relevant for RESET when nRESET active and filling f0272
// the pipeline when nRESET deactivated f0273
// f0274
//-------------------------------------------------------------------------- f0275
f0276
// f0277
// Reset PCU f0278
// f0279
always @(nRESET) begin f0280
while (~nRESET) begin f0281
DO_STARTUP = 1'b1; f0282
NEXT_KUMODE = 1'b1; f0283
NEXT_HWIACT = 1'b1; f0284
NEXT_EXCACT = 1'b1; f0285
NEXT_SWIACT = 1'b1; f0286
IF_KUMODE = 1'b1; f0287
IF_HWIACT = 1'b1; f0288
IF_EXCACT = 1'b1; f0289
IF_SWIACT = 1'b1; f0290
ID_KUMODE = 1'b1; f0291
ID_HWIACT = 1'b1; f0292
ID_EXCACT = 1'b1; f0293
ID_SWIACT = 1'b1; f0294
PANIC = 1'b0; f0295
FLAGS = 4'b0; f0296
MAU_OPCODE3 = 3'b100; f0297
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