3_07pcu

大型risc处理器设计源代码,这是书中的代码 基于流水线的risc cpu设计

//----------------------------------------------------------------------------   f0000
//                                                                               f0001
// PCU: module of pipeline control unit                                          f0002
//                                                                               f0003
// Tasks: work FIFO, MAU instruction delay, memory access allocation,            f0004
//        interrupt control, handling of special register VBR                    f0005
//        (vector base register), SR (status register), ISRs                     f0006
//        (interrupt status register), return PC, interrupt                      f0007
//        return PCs, and interrupt addresses                                    f0008
//                                                                               f0009
// Signal encodings:                                                             f0010
//  SREG_ADDR:     0000: PC     (program counter)                                f0011
//                 0001: RPC    (return PC)                                      f0012
//                 0010: LPC    (last PC)                                        f0013
//                 0011: SR     (status register)                                f0014
//                 0101: VBR    (interrupt vector base register)                 f0015
//                 0110: HISR   (hardware interrupt status register)             f0016
//                 0111: ECSR   (exception status register)                      f0017
//                 1000: SISR   (software interrupt status register)             f0018
//                 1001: HIRPC  (hardware interrupt return PC)                   f0019
//                 1010: ECRPC  (exception return PC)                            f0020
//                 1011: SIRPC  (software interrupt return PC)                   f0021
//                 1100: HIADR  (memory address in case of HWI)                  f0022
//                 1101: ECADR  (instruction address in case of exception)       f0023
//  MAU_ACC_MODEx:  0??: byte access                                             f0024
//                  1?0: halfword access                                         f0025
//                  1?1: word access                                             f0026
//  MAU_OPCODEx:    00?: MAU read access                                         f0027
//                  010: MAU write access                                        f0028
//                  011: MAU swap access                                         f0029
//                  1??: no MAU access                                           f0030
//  BCU_ACC_MODE:   000: MAU byte access                                         f0031
//                  001: MAU halfword access                                     f0032
//                  010: MAU word access                                         f0033
//                  110: IFU fetch access                                        f0034
//  BCU_ACC_DIR:     00: read data                                               f0035
//                   01: write data                                              f0036
//                   10: swap                                                    f0037
//  INT_STATE:       00: no interrupt overlay register set                       f0038
//                   01: EXC/SWI overlay register set superimposed               f0039
//                   1?: hardware interrupt overlay register set superimposed    f0040
//  xx_STATUS:    bit 0: carry flag         \                                    f0041
//                bit 1: overflow flag       | flags                             f0042
//                bit 2: zero flag           |                                   f0043
//                bit 3: negative flag      /                                    f0044
//                bit 4: SWI status         \                                    f0045
//                bit 5: EXC status          | mode                              f0046
//                bit 6: HWI status          |                                   f0047
//                bit 7: kernel/user status /                                    f0048
//                                                                               f0049
//----------------------------------------------------------------------------   f0050
                                                                                 f0051
module pcu (                                                                     f0052
    SREG_DATA, IF_FLAGS, FD_FLAGS, ALU_CARRY,                                    f0053
    PC_BUS,                                                                      f0054
    MAU_ACC_MODE3, MAU_OPCODE3, BCU_ACC_MODE, BCU_ACC_DIR, INT_STATE,            f0055
    nIRA, SYS_KUMODE, IF_KUMODE, ID_KUMODE, STEP,                                f0056
    WORK_IF, WORK_FD, WORK_ID, WORK_EX, WORK_MA, WORK_WB,                        f0057
    USE_PCU_PC, LDST_ACC_NOW, EMERG_FETCH, KILL_IDU,                             f0058
    B_BUS, FLAGS_FROM_ALU, SWI_ID, IRQ_ID, EXCEPT_ID,                            f0059
    MAU_ADDR_BUS, IFU_ADDR_BUS, NPC, SREG_ADDR, MAU_ACC_MODE2, MAU_OPCODE2,      f0060
    CP, nRESET, nIRQ, BCU_READY,                                                 f0061
    CALL_NOW, IFU_CORRECT, DS_IN_IFU, DIS_IDU, DIS_ALU,                          f0062
    SREG_ACC_DIR, SWI_RQ, EXCEPT_RQ, DO_HALT, DO_RETI, NEW_FLAGS                 f0063
  );                                                                             f0064
                                                                                 f0065
  // Outputs                                                                     f0066
  output [31:0] SREG_DATA;       // data from special register                   f0067
  output [ 3:0] IF_FLAGS,        // flags for IF branch decision                 f0068
                FD_FLAGS;        // flags for FD branch decision                 f0069
  output        ALU_CARRY;       // carry operand for ALU                        f0070
  output [31:2] PC_BUS;          // bus for PC transfer to IFU                   f0071
  output [ 2:0] MAU_ACC_MODE3,   // access width for MAU                         f0072
                MAU_OPCODE3,     // opcode for MAU                               f0073
                BCU_ACC_MODE;    // BCU access unit (IFU/MAU) and width          f0074
  output [ 1:0] BCU_ACC_DIR,     // BCU access direction                         f0075
                INT_STATE;       // interrupt overlay register set selection     f0076
  output        nIRA,            // interrupt acknowledge to system              f0077
                SYS_KUMODE,      // kernel/user mode for system accesses         f0078
                IF_KUMODE,       // kernel/user mode for IF                      f0079
                ID_KUMODE,       // kernel/user mode for ID                      f0080
                STEP,            // pipeline enable                              f0081
                WORK_IF,         // work enable for IF stage                     f0082
                WORK_FD,         // work enable for FD stage                     f0083
                WORK_ID,         // work enable for ID stage                     f0084
                WORK_EX,         // work enable for EX stage                     f0085
                WORK_MA,         // work enable for MA stage                     f0086
                WORK_WB,         // work enable for WB stage                     f0087
                USE_PCU_PC,      // ask IFU to take PC_BUS                       f0088
                LDST_ACC_NOW,    // inform IFU on MAU memory access              f0089
                EMERG_FETCH,     // IFU has to fetch in next step                f0090
                KILL_IDU;        // disable IDU                                  f0091
                                                                                 f0092
  // Inputs                                                                      f0093
  input  [31:0] B_BUS;           // operand bus B                                f0094
  input  [ 3:0] FLAGS_FROM_ALU,  // flags from ALU                               f0095
                SWI_ID;          // SWI code from IDU                            f0096
  input  [ 2:0] IRQ_ID,          // system interrupt request code                f0097
                EXCEPT_ID;       // exception code from IDU                      f0098
  input  [31:0] MAU_ADDR_BUS;    // MAU memory access address                    f0099
  input  [31:2] IFU_ADDR_BUS,    // fetch PC from IFU (memory access address)    f0100
                NPC;             // next PC from IFU (return PC for CALL and SWI)f0101
  input  [ 3:0] SREG_ADDR;       // special register address from IDU            f0102
  input  [ 2:0] MAU_ACC_MODE2,   // access width and mode for MA from IDU        f0103
                MAU_OPCODE2;     // opcode for MA                                f0104
  input         CP,              // processor clock                              f0105
                nRESET,          // reset                                        f0106
                nIRQ,            // system interrupt request                     f0107
                BCU_READY,       // no memory access in progress                 f0108
                CALL_NOW,        // CALL instruction in ID                       f0109
                IFU_CORRECT,     // IFU corrects branch decision                 f0110
                DS_IN_IFU,       // CTR in ID and delay instruction in IF        f0111
                DIS_IDU,         // disable IDU                                  f0112
                DIS_ALU,         // disable ALU                                  f0113
                SREG_ACC_DIR,    // access direction for special register        f0114
                SWI_RQ,          // IDU requests SWI                             f0115
                EXCEPT_RQ,       // IDU requests exception                       f0116
                DO_HALT,         // IDU decoded HALT                             f0117
                DO_RETI,         // IDU decoded RETI                             f0118
                NEW_FLAGS;       // flag changing ALU instruction in ID (.F)     f0119
                                                                                 f0120
  // Registers for outputs                                                       f0121
  reg   [31:0]  SREG_DATA;       // data from special register                   f0122
  reg   [31:2]  PC_BUS;          // bus for PC transfer to IFU                   f0123
  reg   [ 2:0]  MAU_ACC_MODE3,   // access width for MAU                         f0124
                MAU_OPCODE3,     // opcode for MAU                               f0125
                BCU_ACC_MODE;    // BCU access unit (IFU/MAU) and width          f0126
  reg   [ 1:0]  BCU_ACC_DIR;     // BCU access direction                         f0127
  reg           nIRA,            // interrupt acknowledge to system              f0128
                SYS_KUMODE,      // kernel/user mode for system accesses         f0129
                IF_KUMODE,       // kernel/user mode for IF                      f0130
                ID_KUMODE,       // kernel/user mode for ID                      f0131
                USE_PCU_PC,      // ask IFU to take PC_BUS                       f0132
                EMERG_FETCH;     // IFU has to fetch in next step                f0133
                                                                                 f0134
  // Wires for outputs                                                           f0135
  wire          WORK_IF,         // work enable for stage IF                     f0136
                WORK_FD,         // work enable for stage FD                     f0137
                WORK_ID,         // work enable for stage ID                     f0138
                WORK_EX,         // work enable for stage EX                     f0139
                WORK_MA,         // work enable for stage MA                     f0140
                WORK_WB;         // work enable for stage WB                     f0141
                                                                                 f0142
  // Wires for inputs                                                            f0143
  wire   [31:0] B_BUS;           // operand bus B                                f0144
  wire   [ 3:0] FLAGS_FROM_ALU,  // flags from ALU                               f0145
                SWI_ID;          // SWI code from IDU                            f0146
  wire   [ 2:0] IRQ_ID,          // system interrupt request code                f0147
                EXCEPT_ID;       // exception code from IDU                      f0148