3_09syst

大型risc处理器设计源代码,这是书中的代码 基于流水线的risc cpu设计

//  'misalign'  (ID=001), if invalid address for data width                      s0596
//                                                                               s0597
// Wait states in memory access:                                                 s0598
//   `define WAITSTATE specifies the number of wait cycles                       s0599
//   when accessing a bank (8'bB3B2B1B0):                                        s0600
//     Bx: number of wait cycles for bank x (binary encoded)                     s0601
//                                                                               s0602
//----------------------------------------------------------------------------   s0603
                                                                                 s0604
module syscon (IRQ_ID, CP, nRESET, nIRQ, nMHS,                                   s0605
               nRAM_SEL0, nRAM_SEL1, nRAM_SEL2, nRAM_SEL3, nROM_SEL,             s0606
               SYS_DATA_BUS, ADDR_BUS, ACMD, nIRA, MRnW, nMRQ, KUMODE);          s0607
                                                                                 s0608
  // Outputs                                                                     s0609
  output [ 2:0] IRQ_ID;            // interrupt ID                               s0610
  output        CP,                // system clock                               s0611
                nRESET,            // reset                                      s0612
                nIRQ,              // interrupt request                          s0613
                nMHS,              // memory handshake                           s0614
                nRAM_SEL0,         // RAM bits 7-0                               s0615
                nRAM_SEL1,         // RAM bits 15-8                              s0616
                nRAM_SEL2,         // RAM bits 23-16                             s0617
                nRAM_SEL3,         // RAM bits 31-24                             s0618
                nROM_SEL;          // ROM                                        s0619
                                                                                 s0620
  // Inputs                                                                      s0621
  input  [31:0] SYS_DATA_BUS,      // system data bus                            s0622
                ADDR_BUS;          // address bus                                s0623
  input  [ 1:0] ACMD;              // memory access mode                         s0624
  input         nIRA,              // interrupt acknowledge                      s0625
                MRnW,              // memory read/write                          s0626
                nMRQ,              // memory request                             s0627
                KUMODE;            // kernel/user mode                           s0628
                                                                                 s0629
  reg           CP,                // system clock                               s0630
                nRESET;            // reset                                      s0631
                                                                                 s0632
  wire   [ 2:0] IRQ_ID;            // interrupt ID                               s0633
  wire          nIRQ,              // interrupt request                          s0634
                nMHS,              // memory handshake                           s0635
                nRAM_SEL0,         // RAM bits 7-0                               s0636
                nRAM_SEL1,         // RAM bits 15-8                              s0637
                nRAM_SEL2,         // RAM bits 23-16                             s0638
                nRAM_SEL3,         // RAM bits 31-24                             s0639
                nROM_SEL;          // ROM                                        s0640
  wire   [31:0] SYS_DATA_BUS,      // system data bus                            s0641
                ADDR_BUS;          // address bus                                s0642
  wire   [ 1:0] ACMD;              // memory access mode                         s0643
  wire          nIRA,              // interrupt acknowledge                      s0644
                MRnW,              // memory read/write                          s0645
                nMRQ,              // memory request                             s0646
                KUMODE;            // kernel/user mode                           s0647
                                                                                 s0648
  reg           CP2;               // timer clock (twice system clock)           s0649
                                                                                 s0650
  wire          ROM_REMAP,         // bank 0: 0 = RAM, 1 = ROM                   s0651
                BEI_RQ,            // bus error interrupt request                s0652
                MAI_RQ,            // misalign interrupt request                 s0653
                PFI_RQ,            // page fault interrupt request               s0654
                TMI_RQ,            // timer interrupt request                    s0655
                nIO_SEL0,          // I/O selection (USER page FIFO)             s0656
                nIO_SEL1;          // I/O selection (timer register)             s0657
                                                                                 s0658
  //                                                                             s0659
  // Instances                                                                   s0660
  //                                                                             s0661
                                                                                 s0662
  // ROM_REMAP generator                                                         s0663
  map_gen MAP_GEN(ROM_REMAP, ADDR_BUS[31:30], nMRQ, nRESET);                     s0664
                                                                                 s0665
  // Memory handshake generator                                                  s0666
  mhs_gen MHS_GEN(nMHS, ADDR_BUS[31:30], MRnW, nMRQ, CP, ROM_REMAP);             s0667
                                                                                 s0668
  // Bus error interrupt generator                                               s0669
  bei_gen BEI_GEN(BEI_RQ, ADDR_BUS[31:30], MRnW, nMRQ, KUMODE, ROM_REMAP);       s0670
                                                                                 s0671
  // Misalign interrupt generator                                                s0672
  mai_gen MAI_GEN(MAI_RQ, ADDR_BUS[1:0], ACMD, nMRQ);                            s0673
                                                                                 s0674
  // Selection generator                                                         s0675
  sel_gen SEL_GEN(nROM_SEL, nIO_SEL0, nIO_SEL1,                                  s0676
                  nRAM_SEL0, nRAM_SEL1, nRAM_SEL2, nRAM_SEL3,                    s0677
                  ADDR_BUS[2:0], ADDR_BUS[31:30],                                s0678
                  ACMD, ROM_REMAP, nMHS, BEI_RQ, MAI_RQ, PFI_RQ);                s0679
                                                                                 s0680
  // Page fault interrupt generator                                              s0681
  pfi_gen PFI_GEN(PFI_RQ, SYS_DATA_BUS[31:8], ADDR_BUS[31:8],                    s0682
                  MRnW, nMRQ, KUMODE, nIO_SEL0);                                 s0683
                                                                                 s0684
  // Timer interrupt generator                                                   s0685
  tmi_gen TMI_GEN(TMI_RQ, SYS_DATA_BUS[15:0], MRnW, CP2, nRESET, nIO_SEL1);      s0686
                                                                                 s0687
  // Interrupt generator                                                         s0688
  int_gen INT_GEN(IRQ_ID, nIRQ,                                                  s0689
                  CP2, nIRA, nMRQ, PFI_RQ, BEI_RQ, MAI_RQ, TMI_RQ);              s0690
                                                                                 s0691
                                                                                 s0692
  //                                                                             s0693
  // Generation of system clock, timer, interrupt clock                          s0694
  //                                                                             s0695
  always begin                                                                   s0696
    CP  = 1'b1;                                                                  s0697
    CP2 = 1'b1;                                                                  s0698
    #`QUAD_CYCLE;                                                                s0699
    CP2 = 1'b0;                                                                  s0700
    #`QUAD_CYCLE;                                                                s0701
    CP  = 1'b0;                                                                  s0702
    CP2 = 1'b1;                                                                  s0703
    #`QUAD_CYCLE;                                                                s0704
    CP2 = 1'b0;                                                                  s0705
    #`QUAD_CYCLE;                                                                s0706
  end                                                                            s0707
                                                                                 s0708
  //                                                                             s0709
  // RESET after power on                                                        s0710
  //                                                                             s0711
  initial begin                                                                  s0712
    nRESET = 1'b0;                                                               s0713
    #`RESET_TIME;                                                                s0714
    nRESET = 1'b1;                                                               s0715
  end                                                                            s0716
                                                                                 s0717
endmodule // syscon                                                              s0718
                                                                                 s0719
                                                                                 s0720
//----------------------------------------------------------------------------   s0721
//                                                                               s0722
// map_gen (ROM_REMAP generator)                                                 s0723
//                                                                               s0724
// Enable ROM_REMAP during reset, disable with                                   s0725
// first access to memory bank 3 after reset                                     s0726
//                                                                               s0727
//----------------------------------------------------------------------------   s0728
                                                                                 s0729
module map_gen (ROM_REMAP, BANK_ID, nMRQ, nRESET);                               s0730
                                                                                 s0731
  output       ROM_REMAP;          // ROM_REMAP                                  s0732
  input  [1:0] BANK_ID;            // memory bank number                         s0733
  input        nMRQ,               // memory request                             s0734
               nRESET;             // reset                                      s0735
                                                                                 s0736
  reg          ROM_REMAP;          // ROM_REMAP                                  s0737
  wire   [1:0] BANK_ID;            // memory bank number                         s0738
  wire         nMRQ,               // memory request                             s0739
               nRESET;             // reset                                      s0740
                                                                                 s0741
  always @(posedge nRESET)                                                       s0742
    ROM_REMAP = 1'b1;                                                            s0743