3_09syst

大型risc处理器设计源代码,这是书中的代码 基于流水线的risc cpu设计

// clktm (clock timer)                                                           s0447
//                                                                               s0448
// Number of clock cycles since system start (read only)                         s0449
//                                                                               s0450
//----------------------------------------------------------------------------   s0451
                                                                                 s0452
module clktm (DATA_BUS, ADDR_BUS, MRnW, nMRQ, nMHS);                             s0453
                                                                                 s0454
  parameter     SYS_ADDR = 32'h80000008; // system address of clock timer        s0455
                                                                                 s0456
  output [31:0] DATA_BUS;                // data output                          s0457
                                                                                 s0458
  input  [31:0] ADDR_BUS;                // address bus                          s0459
  input         MRnW,                    // memory read/write of CPU             s0460
                nMRQ,                    // memory request of CPU                s0461
                nMHS;                    // memory handshake of periphery        s0462
                                                                                 s0463
                                                                                 s0464
  reg    [31:0] DATA_DRV;                // data driver                          s0465
  wire   [31:0] DATA_BUS = DATA_DRV;     // data bus                             s0466
  wire   [31:0] ADDR_BUS;                // address bus                          s0467
  wire          MRnW,                    // memory read/write of CPU             s0468
                nMHQ,                    // memory request of CPU                s0469
                nMHS;                    // memory handshake of periphery        s0470
                                                                                 s0471
  initial DATA_DRV = 32'bz;              // driver disabled                      s0472
                                                                                 s0473
  always @(nMRQ) begin                                                           s0474
    if (!nMRQ && ADDR_BUS == SYS_ADDR) begin // clock timer request              s0475
      if (MRnW) begin                        // system time is read              s0476
        wait(!nMRQ && !nMHS);                // bus free                         s0477
        if (ADDR_BUS == SYS_ADDR) begin                                          s0478
          DATA_DRV = system.CYCLE_CNT;       // time                             s0479
          wait(nMRQ && nMHS);                // data taken                       s0480
          DATA_DRV = 32'bz;                  // turn off drivers                 s0481
        end                                                                      s0482
      end                                                                        s0483
      else                                   // illegal write access             s0484
        $display(                                                                s0485
          "\nERROR: read only;    Addr = %h\n", ADDR_BUS                         s0486
        );                                                                       s0487
    end                                                                          s0488
  end                                                                            s0489
                                                                                 s0490
endmodule // clktm                                                               s0491
                                                                                 s0492
                                                                                 s0493
//----------------------------------------------------------------------------   s0494
//                                                                               s0495
// buscnv (bus converter)                                                        s0496
//                                                                               s0497
// Adaptation of asynchronous system bus protocol                                s0498
// to actual processor bus protocol                                              s0499
//                                                                               s0500
//----------------------------------------------------------------------------   s0501
                                                                                 s0502
module buscnv (CPU_DATA, SYS_DATA, CP, BUSPRO, MRnW, nMHS);                      s0503
                                                                                 s0504
  inout [31:0] CPU_DATA,           // processor data bus                         s0505
               SYS_DATA;           // system data bus                            s0506
                                                                                 s0507
  input        CP,                 // system clock                               s0508
               BUSPRO,             // protocol                                   s0509
               MRnW,               // memory read/write                          s0510
               nMHS;               // memory handshake                           s0511
                                                                                 s0512
  reg   [31:0] CD_REG,             // driver of processor data bus               s0513
               SD_REG;             // driver of system data bus                  s0514
  wire  [31:0] CPU_DATA = CD_REG;  // processor data bus                         s0515
  wire  [31:0] SYS_DATA = SD_REG;  // system data bus                            s0516
  wire         CP,                 // system clock                               s0517
               BUSPRO,             // protocol                                   s0518
               MRnW,               // memory read/write                          s0519
               nMHS;               // memory handshake                           s0520
                                                                                 s0521
  //                                                                             s0522
  // For asynchronous protocol, connect data                                     s0523
  // buses according to data direction;                                          s0524
  //                                                                             s0525
  // for synchronous protocol, latch read data during                            s0526
  // nMHS low and write data in second half of clock;                            s0527
  //                                                                             s0528
  // in the synchronous case, access wait time                                   s0529
  // has to be greater than half a clock                                         s0530
  //                                                                             s0531
  always @(CP or BUSPRO or MRnW or nMHS or CPU_DATA or SYS_DATA) begin           s0532
    if (MRnW) begin                                                              s0533
      SD_REG = {32{1'bz}};                                                       s0534
      if (BUSPRO) begin                                                          s0535
        if (~nMHS) CD_REG = SYS_DATA;                                            s0536
      end                                                                        s0537
      else if (~nMHS | CP) CD_REG = SYS_DATA;                                    s0538
    end                                                                          s0539
    else begin                                                                   s0540
      CD_REG = {32{1'bz}};                                                       s0541
      if (BUSPRO) begin                                                          s0542
        if (~CP) SD_REG = CPU_DATA;                                              s0543
      end                                                                        s0544
      else SD_REG = CPU_DATA;                                                    s0545
    end                                                                          s0546
  end                                                                            s0547
                                                                                 s0548
endmodule // buscnv                                                              s0549
                                                                                 s0550
                                                                                 s0551
//----------------------------------------------------------------------------   s0552
//                                                                               s0553
// syscon (system controller)                                                    s0554
//                                                                               s0555
// - memory control and memory protection                                        s0556
// - interrupt control                                                           s0557
// - interrupt timer                                                             s0558
// - reset logic                                                                 s0559
// - system clock generator                                                      s0560
//                                                                               s0561
//                                                                               s0562
// Memory partitioning:                                                          s0563
//                                                                               s0564
// bank  address       after reset              after first access to bank 3     s0565
//                                                                               s0566
//   3   $FFFFFFFF     ROM                      ROM                              s0567
//       $C0000000_    (only KERNEL access)     (only KERNEL access)             s0568
//                                                                               s0569
//   2   $BFFFFFFF     I/O                      I/O                              s0570
//       $80000000_    (only KERNEL access)     (only KERNEL access)             s0571
//                                                                               s0572
//   1   $7FFFFFFF     RAM                      RAM                              s0573
//       $40000000_    (only KERNEL access)     (only KERNEL access)             s0574
//                                                                               s0575
//   0   $3FFFFFFF     ROM                      RAM (USER access to              s0576
//       $00000000_    (only KERNEL access)          allowed pages only)         s0577
//                                                                               s0578
// I/O area: organized word-wise, write-only, not readable                       s0579
//                                                                               s0580
// A2=0: first element of USER page FIFO of                                      s0581
//       length 3 containing three page numbers                                  s0582
//       allowed for user accesses (bits 31-8);                                  s0583
//       with each entry, the FIFO is shifted by one,                            s0584
//       the last element is shifted out of FIFO;                                s0585
//       violation 'page fault' (ID=001)                                         s0586
//                                                                               s0587
//    1: interrupt timer control (bits 15-0):                                    s0588
//        bit 15:   timer mode (0 = count down, 1 = modulo)                      s0589
//        bit 14-0: number of clock cycles until interrupt times four            s0590
//        time-out 'interrupt 3' (ID=011)                                        s0591
//                                                                               s0592
// Other hardware interrupts:                                                    s0593
//  'bus error' (ID=000), if write access to ROM                                 s0594
//              or USER access to KERNEL memory area                             s0595