📄 3_09syst
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// the memory consists of 4 RAMs, s0149
// which are not organized as instances, s0150
// but as a linear array to enable initialization s0151
// with 32-bit words using $readmem; s0152
// s0153
//---------------------------------------------------------------------------- s0154
s0155
module ram (RAM_DATA, RAM_ADDR, RAM_RnW, nRAMS0, nRAMS1, nRAMS2, nRAMS3, nSEL); s0156
s0157
parameter WC = 13; // word count = number of address lines s0158
// default 13 => 2^13 = 8K = 32KB s0159
s0160
inout [31:0] RAM_DATA; // system data bus s0161
s0162
input [27:0] RAM_ADDR; // RAM address bus (word) s0163
input RAM_RnW, // RAM read/write s0164
nRAMS0, // RAM selection bits 0-7 s0165
nRAMS1, // RAM selection bits 8-15 s0166
nRAMS2, // RAM selection bits 16-23 s0167
nRAMS3, // RAM selection bits 24-31 s0168
nSEL; // RAM enable s0169
s0170
reg [31:0] DATA_DRV; // data output driver s0171
wire [31:0] RAM_DATA = DATA_DRV; // data bus s0172
wire [27:0] RAM_ADDR; // address bus (word address) s0173
wire RAM_RnW, // RAM read/write s0174
nRAMS0, // RAM selection bits 0-7 s0175
nRAMS1, // RAM selection bits 8-15 s0176
nRAMS2, // RAM selection bits 16-23 s0177
nRAMS3, // RAM selection bits 24-31 s0178
nSEL; // RAM enable s0179
s0180
reg [31:0] MEMORY[0:(1<<WC)-1], // memory s0181
MEMWORD; // temporary word register for accesses s0182
integer TIMER_0, // access time for bits 0-7 s0183
TIMER_1, // access time for bits 8-15 s0184
TIMER_2, // access time for bits 16-23 s0185
TIMER_3; // access time for bits 24-31 s0186
s0187
// s0188
// Load memory with test program and data s0189
// s0190
initial begin s0191
// s0192
// RAM size between s0193
// 1KB and 64MB s0194
// s0195
if (( WC < 8 ) || ( WC > 24) ) begin s0196
$display("FATAL ERROR:\n%m: wrong RAM size\n"); s0197
$finish(2); s0198
end s0199
// s0200
// Load program s0201
// s0202
if (`PRG_FORMAT) $readmemh(`PROGRAM, MEMORY); s0203
else $readmemb(`PROGRAM, MEMORY); s0204
end s0205
s0206
// s0207
// Byte group 0 (bits 7-0) active; s0208
// perform access after access wait time s0209
// s0210
always @(TIMER_0) begin s0211
if ((nRAMS0 == 1'b0) && (nSEL == 1'b0) && (TIMER_0 == 0)) s0212
begin s0213
if ((`CHK_HGH_BITs == 1) && (RAM_ADDR[27:WC] != 0)) s0214
begin s0215
$display( s0216
"\nERROR: Addr invalid; Addr = --%b--\n", RAM_ADDR s0217
); s0218
$stop(2); s0219
end s0220
MEMWORD = MEMORY[RAM_ADDR[WC-1:0]]; s0221
if (RAM_RnW == 1'b1) DATA_DRV[ 7: 0] = MEMWORD[ 7: 0]; s0222
else MEMWORD[ 7: 0] = RAM_DATA[ 7: 0]; s0223
MEMORY[RAM_ADDR[WC-1:0]] = MEMWORD; s0224
end s0225
end s0226
s0227
// s0228
// Byte group 1 (bits 15-8) active; s0229
// perform access after access wait time; s0230
// if address outside RAM, stop system s0231
// s0232
always @(TIMER_1) begin s0233
if ((nRAMS1 == 1'b0) && (nSEL == 1'b0) && (TIMER_1 == 0)) s0234
begin s0235
if ((`CHK_HGH_BITs == 1) && (RAM_ADDR[27:WC] != 0)) s0236
begin s0237
$display( s0238
"\nERROR: Addr invalid; Addr = --%b--\n", RAM_ADDR s0239
); s0240
$stop(2); s0241
end s0242
MEMWORD = MEMORY[RAM_ADDR[WC-1:0]]; s0243
if (RAM_RnW == 1'b1) DATA_DRV[15: 8] = MEMWORD[15: 8]; s0244
else MEMWORD[15: 8] = RAM_DATA[15: 8]; s0245
MEMORY[RAM_ADDR[WC-1:0]] = MEMWORD; s0246
end s0247
end s0248
s0249
// s0250
// Byte group 2 (bits 23-16) active; s0251
// perform access after access wait time s0252
// s0253
always @(TIMER_2) begin s0254
if ((nRAMS2 == 1'b0) && (nSEL == 1'b0) && (TIMER_2 == 0)) s0255
begin s0256
if ((`CHK_HGH_BITs == 1) && (RAM_ADDR[27:WC] != 0)) s0257
begin s0258
$display( s0259
"\nERROR: Addr invalid; Addr = **%b**\n", RAM_ADDR s0260
); s0261
$stop(2); s0262
end s0263
MEMWORD = MEMORY[RAM_ADDR[WC-1:0]]; s0264
if (RAM_RnW == 1'b1) DATA_DRV[23:16] = MEMWORD[23:16]; s0265
else MEMWORD[23:16] = RAM_DATA[23:16]; s0266
MEMORY[RAM_ADDR[WC-1:0]] = MEMWORD; s0267
end s0268
end s0269
s0270
// s0271
// Byte group 3 (bits 31-24) active; s0272
// perform access after access wait time s0273
// s0274
always @(TIMER_3) begin s0275
if ((nRAMS3 == 1'b0) && (nSEL == 1'b0) && (TIMER_3 == 0)) s0276
begin s0277
if ((`CHK_HGH_BITs == 1) && (RAM_ADDR[27:WC] != 0)) s0278
begin s0279
$display( s0280
"\nERROR: Addr invalid; Addr = **%b**\n", RAM_ADDR s0281
); s0282
$stop(2); s0283
end s0284
MEMWORD = MEMORY[RAM_ADDR[WC-1:0]]; s0285
if (RAM_RnW == 1'b1) DATA_DRV[31:24] = MEMWORD[31:24]; s0286
else MEMWORD[31:24] = RAM_DATA[31:24]; s0287
MEMORY[RAM_ADDR[WC-1:0]] = MEMWORD; s0288
end s0289
end s0290
s0291
// s0292
// Count down access wait time s0293
// synchronously with simulation time s0294
// s0295
always #1 if ((nRAMS0 == 1'b0) && (nSEL == 1'b0) && (TIMER_0 > 0)) s0296
TIMER_0 = TIMER_0 - 1; s0297
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