3_09syst

大型risc处理器设计源代码,这是书中的代码 基于流水线的risc cpu设计

//----------------------------------------------------------------------------   s0000
//                                                                               s0001
// SYSTEM: test environment of TOOBSIE consisting of processor,                  s0002
//         operating system in ROM, RAM, and system controller                   s0003
//         with memory control and interrupt timer                               s0004
//                                                                               s0005
// Instances:                                                                    s0006
//   CHIP     processor                                                          s0007
//   RAM      user RAM                                                           s0008
//   KRAM     kernel RAM                                                         s0009
//   ROM      ROM                                                                s0010
//   CLKTM    clock timer                                                        s0011
//   BUSCNV   data bus protocol converter                                        s0012
//   SYSCON   system controller                                                  s0013
//                                                                               s0014
// Set cache configuration;                                                      s0015
// set bus protocol                                                              s0016
//                                                                               s0017
// Signal definitions for names not self-explaining:                             s0018
//   ACMD:   00: byte access                                                     s0019
//           01: halfword access                                                 s0020
//           10: word access                                                     s0021
//   IRQ_ID: 000: bus error                                                      s0022
//           001: page fault                                                     s0023
//           010: misalign                                                       s0024
//           011: timer                                                          s0025
//           1XX: unused                                                         s0026
//   CONFIG: 00000: both caches off                                              s0027
//           0XX01: BTC (BCC only), parallel mode                                s0028
//           0XX10: BTC (CALL only), parallel mode                               s0029
//           0XX11: BTC (BCC and CALL), parallel mode                            s0030
//           001XX: RIB, parallel mode                                           s0031
//           010XX: IC, parallel mode                                            s0032
//           X11XX: reserved                                                     s0033
//           1XXXX: serial mode                                                  s0034
//   BUSPRO: 0: asynchronous bus protocol                                        s0035
//           1: synchronous bus protocol                                         s0036
//   FACC:   0: data access                                                      s0037
//           1: instruction access                                               s0038
//   KUMODE: 0: USER                                                             s0039
//           1: KERNEL                                                           s0040
//                                                                               s0041
//----------------------------------------------------------------------------   s0042
                                                                                 s0043
module system;                                                                   s0044
                                                                                 s0045
  wire [31:0] CPU_DATA_BUS,       // processor data bus                          s0046
              SYS_DATA_BUS,       // system data bus                             s0047
              ADDR_BUS;           // system address bus                          s0048
  wire [ 2:0] IRQ_ID;             // interrupt identification of CPU             s0049
  wire [ 1:0] ACMD;               // memory access mode of CPU                   s0050
  wire        CP,                 // system clock                                s0051
              nRESET,             // reset of CPU                                s0052
              nIRQ,               // interrupt request of CPU                    s0053
              nIRA,               // interrupt acknowledge of CPU                s0054
              MRnW,               // memory read/write of CPU                    s0055
              nRMW,               // read modify write of CPU                    s0056
              nMRQ,               // memory request of CPU                       s0057
              FACC,               // fetch access of CPU                         s0058
              nMHS,               // memory handshake of CPU                     s0059
              KUMODE,             // kernel/user mode of CPU                     s0060
              nRAM_SEL0,          // RAM activation bits 7-0                     s0061
              nRAM_SEL1,          // RAM activation bits 15-8                    s0062
              nRAM_SEL2,          // RAM activation bits 23-16                   s0063
              nRAM_SEL3,          // RAM activation bits 31-24                   s0064
              nROM_SEL;           // ROM activation                              s0065
  reg  [ 4:0] CONFIG;             // cache configuration                         s0066
  reg         BUSPRO,             // bus protocol of CPU                         s0067
              nHLT;               // halt CPU                                    s0068
  integer     MHS_WAIT,           // length of nMHS without wait cycles          s0069
              CYCLE_CNT;          // clock cycles simulated so far               s0070
                                                                                 s0071
  //                                                                             s0072
  // Instances                                                                   s0073
  //                                                                             s0074
                                                                                 s0075
  // CHIP                                                                        s0076
  chip   CHIP (ADDR_BUS, ACMD, nIRA, MRnW, nRMW, nMRQ, FACC, KUMODE,             s0077
               CPU_DATA_BUS,                                                     s0078
               CONFIG, IRQ_ID, CP, nRESET, nIRQ, nMHS, nHLT, BUSPRO);            s0079
                                                                                 s0080
  // RAM                                                                         s0081
  ram    #(`USER_RAM_SIZE)                                                       s0082
         RAM (SYS_DATA_BUS, ADDR_BUS[29:2],                                      s0083
              MRnW, nRAM_SEL0, nRAM_SEL1, nRAM_SEL2, nRAM_SEL3, ADDR_BUS[30]);   s0084
                                                                                 s0085
  // RAM                                                                         s0086
  ram    #(`KERNEL_RAM_SIZE)                                                     s0087
         KRAM (SYS_DATA_BUS, ADDR_BUS[29:2],                                     s0088
               MRnW, nRAM_SEL0, nRAM_SEL1, nRAM_SEL2, nRAM_SEL3, ~ADDR_BUS[30]); s0089
                                                                                 s0090
  // ROM                                                                         s0091
  rom    #(`ROM_SIZE)                                                            s0092
         ROM (SYS_DATA_BUS, ADDR_BUS[29:2], nROM_SEL);                           s0093
                                                                                 s0094
  // Clock timer                                                                 s0095
  clktm  #(32'h80000008)                                                         s0096
         CLKTM (SYS_DATA_BUS, ADDR_BUS, MRnW, nMRQ, nMHS);                       s0097
                                                                                 s0098
  // Bus converter                                                               s0099
  buscnv BUSCNV (CPU_DATA_BUS, SYS_DATA_BUS, CP, BUSPRO, MRnW, nMHS);            s0100
                                                                                 s0101
  // System controller                                                           s0102
  syscon SYSCON (IRQ_ID, CP, nRESET, nIRQ, nMHS,                                 s0103
                 nRAM_SEL0, nRAM_SEL1, nRAM_SEL2, nRAM_SEL3, nROM_SEL,           s0104
                 SYS_DATA_BUS, ADDR_BUS, ACMD, nIRA, MRnW, nMRQ, KUMODE);        s0105
                                                                                 s0106
                                                                                 s0107
  //                                                                             s0108
  // Set cache configuration and bus protocol,                                   s0109
  // disable nHLT                                                                s0110
  //                                                                             s0111
  initial begin                                                                  s0112
    CONFIG = {`SERIAL_MODE, `IC_MODE, `RIB_MODE, `BTC_CALL, `BTC_BCC};           s0113
    BUSPRO = `PROTOCOL;                                                          s0114
    nHLT   = 1'b1;                                                               s0115
  end                                                                            s0116
                                                                                 s0117
  //                                                                             s0118
  // Initialize CYCLE_CNT to 0                                                   s0119
  //                                                                             s0120
  initial CYCLE_CNT = 0;                                                         s0121
                                                                                 s0122
  //                                                                             s0123
  // Stop simulation                                                             s0124
  //                                                                             s0125
  always @(posedge CP) begin                                                     s0126
    if (CYCLE_CNT <= `MAX_CYCLES)  CYCLE_CNT = CYCLE_CNT + 1;                    s0127
    else begin                                                                   s0128
      $display("\nTimeout %0d %0d",CYCLE_CNT,`MAX_CYCLES);                       s0129
      $stop(2);                                                                  s0130
    end                                                                          s0131
  end                                                                            s0132
                                                                                 s0133
  //                                                                             s0134
  // For DMA interleave (DMAILEAVE = 1)                                          s0135
  // toggle nHLT with falling clock edge                                         s0136
  //                                                                             s0137
  always @(negedge CP)                                                           s0138
    if (`DMAILEAVE) nHLT = ~nHLT;                                                s0139
                                                                                 s0140
endmodule // system                                                              s0141
                                                                                 s0142
                                                                                 s0143
//----------------------------------------------------------------------------   s0144
//                                                                               s0145
// RAM                                                                           s0146
//                                                                               s0147
// 8K 32-bit memory with definable access time;                                  s0148