📄 3_03idu
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//-------------------------------------------------------------------------- b0272
// b0273
// Decode group DG4 b0274
// b0275
// When instruction register or enable state change, b0276
// update all relevant outputs b0277
// b0278
//-------------------------------------------------------------------------- b0279
b0280
always @(IDU_IREG or IDU_DEREG) begin : DG4 b0281
b0282
// b0283
// Update MAU_OPCODE2 depending on b0284
// instruction class and enable state b0285
// b0286
case({IDU_DEREG, IDU_IREG[31:30]}) b0287
3'b100: MAU_OPCODE2 = {1'b0, IDU_IREG[29:28]}; // MACC instructions b0288
default: MAU_OPCODE2 = {1'b1, IDU_IREG[29:28]}; // else: MAU as buffer b0289
endcase b0290
b0291
// b0292
// Update EXCEPT_ID depending on b0293
// instruction and enable state b0294
// b0295
// Exception code: 000 delayed CTR instruction (requested by IFU) b0296
// 001 privilege violation b0297
// 010 illegal instruction b0298
// 011 unimplemented instruction b0299
// b0300
casez({IDU_DEREG, IDU_IREG[31:24]}) b0301
9'b100??????: EXCEPT_ID = 3'b000; // MACC b0302
9'b101000???: EXCEPT_ID = 3'b000; // ALU (AND, OR) b0303
9'b1010010??: EXCEPT_ID = 3'b000; // ALU (XOR) b0304
9'b10101????: EXCEPT_ID = 3'b000; // ALU (LSL, LSR, ASR, ROT) b0305
9'b10110????: EXCEPT_ID = 3'b000; // ALU (ADD, ADDC, SUB, SUBC) b0306
9'b101111???: EXCEPT_ID = 3'b011; // ALU (MUL, DIV): unimplemented b0307
9'b110??????: EXCEPT_ID = 3'b000; // CALL b0308
9'b11111110?: EXCEPT_ID = 3'b000; // MISC (BRANCH, SWI) b0309
9'b11111111?: EXCEPT_ID = 3'b001; // MISC (RETI, HALT): if, then PV b0310
9'b111100000: EXCEPT_ID = 3'b000; // MISC (LDH) b0311
9'b111100111: EXCEPT_ID = 3'b001; // MISC (CLC): if, then PV b0312
9'b11110101?: EXCEPT_ID = 3'b001; // MISC (LRFS, SRIS): if, then PV b0313
9'b0????????: EXCEPT_ID = 3'b000; // if IDU disabled, then IFU request b0314
default: EXCEPT_ID = 3'b010; // illegal instructions b0315
endcase b0316
b0317
end b0318
b0319
//-------------------------------------------------------------------------- b0320
// b0321
// Decode group DG5 b0322
// b0323
// When instruction register, enable state, b0324
// or processor mode change, b0325
// update all relevant outputs b0326
// b0327
//-------------------------------------------------------------------------- b0328
b0329
always @(IDU_IREG or IDU_DEREG or ID_KUMODE) begin : DG5 b0330
b0331
// b0332
// Set CCLR depending on instruction, b0333
// enable state, and processor mode b0334
// b0335
case({IDU_DEREG, ID_KUMODE, IDU_IREG[31:24]}) b0336
10'b1111100111: CCLR = 1'b1; // valid CLC instruction b0337
default: CCLR = 1'b0; // other instruction b0338
endcase b0339
b0340
// b0341
// Set DO_RETI depending on instruction, b0342
// enable state, and processor mode b0343
// b0344
case({IDU_DEREG, ID_KUMODE, IDU_IREG[31:24]}) b0345
10'b1111111110: DO_RETI = 1'b1; // valid RETI instruction b0346
default: DO_RETI = 1'b0; // other instructions b0347
endcase b0348
b0349
// b0350
// Set DO_HALT depending on instruction, b0351
// enable state, and processor mode b0352
// b0353
case({IDU_DEREG, ID_KUMODE, IDU_IREG[31:24]}) b0354
10'b1111111111: DO_HALT = 1'b1; // valid HALT instruction b0355
default: DO_HALT = 1'b0; // other instructions b0356
endcase b0357
b0358
end b0359
b0360
//-------------------------------------------------------------------------- b0361
// b0362
// Decode group DG6 b0363
// b0364
// When instruction register, enable state, b0365
// input of exception request, processor mode, b0366
// or special register address change, b0367
// update all relevant outputs b0368
// b0369
//-------------------------------------------------------------------------- b0370
b0371
always @(IDU_IREG or IDU_DEREG or b0372
EXCEPT_CTR or ID_KUMODE or ADDR_SREG) begin : DG6 b0373
b0374
// b0375
// Update EXCEPT_RQ depending on instruction, b0376
// enable state, input of exception request, b0377
// processor mode, and special register address b0378
// b0379
casez({IDU_DEREG, IDU_IREG[31:24], ID_KUMODE, (|ADDR_SREG[3:2])}) b0380
11'b100????????: EXCEPT_RQ = 1'b0; // MACC b0381
11'b101000?????: EXCEPT_RQ = 1'b0; // ALU (AND, OR) b0382
11'b1010010????: EXCEPT_RQ = 1'b0; // ALU (XOR) b0383
11'b10101??????: EXCEPT_RQ = 1'b0; // ALU (LSL, LSR, ASR, ROT) b0384
11'b10110??????: EXCEPT_RQ = 1'b0; // ALU (ADD, ADDC, SUB, SUBC) b0385
11'b101111?????: EXCEPT_RQ = 1'b1; // ALU (MUL, DIV): unimplemented b0386
11'b110????????: EXCEPT_RQ = EXCEPT_CTR; // CALL b0387
11'b111111100??: EXCEPT_RQ = EXCEPT_CTR; // MISC (BRANCH) b0388
11'b111111101??: EXCEPT_RQ = EXCEPT_CTR; // MISC (SWI) b0389
11'b11111111?0?: EXCEPT_RQ = 1'b1; // MISC (RETI, HALT): PV b0390
11'b11111111?1?: EXCEPT_RQ = EXCEPT_CTR; // MISC (RETI, HALT) b0391
11'b111100000??: EXCEPT_RQ = 1'b0; // MISC (LDH) b0392
11'b1111001110?: EXCEPT_RQ = 1'b1; // MISC (CLC): PV b0393
11'b1111001111?: EXCEPT_RQ = 1'b0; // MISC (CLC) b0394
11'b11110101?00: EXCEPT_RQ = EXCEPT_CTR; // MISC (LRFS, SRIS) b0395
11'b11110101?01: EXCEPT_RQ = 1'b1; // MISC (LRFS, SRIS): PV b0396
11'b11110101?1?: EXCEPT_RQ = EXCEPT_CTR; // MISC (LRFS, SRIS) b0397
11'b0??????????: EXCEPT_RQ = EXCEPT_CTR; // disable b0398
default: EXCEPT_RQ = 1'b1; // illegal instructions b0399
endcase b0400
b0401
end b0402
b0403
endmodule // idu b0404
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