3_03idu

大型risc处理器设计源代码,这是书中的代码 基于流水线的risc cpu设计

    //                                                                           b0136
    // Update ADDR_B, ADDR_D, SWI_ID,                                            b0137
    // and MAU_ACC_MODE2                                                         b0138
    //                                                                           b0139
    ADDR_B          = IDU_IREG[4:0];                                             b0140
    ADDR_D          = IDU_IREG[23:19];                                           b0141
    SWI_ID          = IDU_IREG[3:0];                                             b0142
    MAU_ACC_MODE2   = IDU_IREG[27:25];                                           b0143
                                                                                 b0144
    //                                                                           b0145
    // Update IMMEDIATE depending on instruction class;                          b0146
    // for MACC instructions, bit 0 is determined from the lowest bit            b0147
    // of access mode in case of a byte access, and bit 1 from the               b0148
    // middle bit in case of no word access (byte or halfword access)            b0149
    //                                                                           b0150
    case(IDU_IREG[31:30])                                                        b0151
      2'b00: begin                                                               b0152
               IMMEDIATE[31:2] = {{16{IDU_IREG[13]}}, IDU_IREG[13:0]};           b0153
               IMMEDIATE[1]    = IDU_IREG[26] & ~(IDU_IREG[25] & IDU_IREG[27]);  b0154
               IMMEDIATE[0]    = IDU_IREG[25] & ~IDU_IREG[27];    // MACC        b0155
             end                                                                 b0156
      2'b11:   IMMEDIATE = {IDU_IREG[18:0], 13'b0};               // MISC        b0157
      default: IMMEDIATE = {{18{IDU_IREG[13]}}, IDU_IREG[13:0]};  // ALU         b0158
    endcase                                                                      b0159
                                                                                 b0160
    //                                                                           b0161
    // Update ADDR_A depending on bit 31 of instruction                          b0162
    // (upper bit of instruction class)                                          b0163
    //                                                                           b0164
    case(IDU_IREG[31])                                                           b0165
      1'b0: ADDR_A = IDU_IREG[18:14];  // ALU and MACC                           b0166
      1'b1: ADDR_A = 5'b0;             // MISC                                   b0167
    endcase                                                                      b0168
                                                                                 b0169
    //                                                                           b0170
    // Update ADDR_SREG depending on bit 24 of instruction                       b0171
    //                                                                           b0172
    casez(IDU_IREG[24])                                                          b0173
      1'b0: ADDR_SREG = IDU_IREG[17:14];   // LRFS (no relevance for others)     b0174
      1'b1: ADDR_SREG = IDU_IREG[22:19];   // SRIS (no relevance for others)     b0175
    endcase                                                                      b0176
                                                                                 b0177
    //                                                                           b0178
    // Update ALU_OPCODE depending on instruction class                          b0179
    //                                                                           b0180
    case(IDU_IREG[31:30])                                                        b0181
      2'b01:   ALU_OPCODE = IDU_IREG[29:26];   // ALU instructions               b0182
      default: ALU_OPCODE = 4'b1000;           // ADD for other instructions     b0183
    endcase                                                                      b0184
                                                                                 b0185
    //                                                                           b0186
    // Update USE_SREG_DATA depending on instruction                             b0187
    //                                                                           b0188
    case(IDU_IREG[31:24])                                                        b0189
      8'b11101010: USE_SREG_DATA = 1'b1;   // LRFS                               b0190
      default:     USE_SREG_DATA = 1'b0;   // other instructions                 b0191
    endcase                                                                      b0192
                                                                                 b0193
    //                                                                           b0194
    // Update USE_IMMEDIATE depending on instruction                             b0195
    //                                                                           b0196
    case(IDU_IREG[31:25])                                                        b0197
      7'b1110101: USE_IMMEDIATE = 1'b0;            // LRFS and SRIS              b0198
      default:    USE_IMMEDIATE = ~IDU_IREG[24];   // other instructions         b0199
    endcase                                                                      b0200
                                                                                 b0201
  end                                                                            b0202
                                                                                 b0203
  //--------------------------------------------------------------------------   b0204
  //                                                                             b0205
  // Decode group DG2                                                            b0206
  //                                                                             b0207
  // When instruction register or exception request change,                      b0208
  // update all relevant outputs                                                 b0209
  //                                                                             b0210
  //--------------------------------------------------------------------------   b0211
                                                                                 b0212
  always @(IDU_IREG or EXCEPT_RQ)  begin : DG2                                   b0213
                                                                                 b0214
    //                                                                           b0215
    // Update ADDR_C depending on instruction                                    b0216
    // and exception request                                                     b0217
    //                                                                           b0218
    casez({EXCEPT_RQ, IDU_IREG[31:24]})                                          b0219
      9'b1????????: ADDR_C = 5'b0;             // exception                      b0220
      9'b00010????: ADDR_C = 5'b0;             // STORE                          b0221
      9'b010??????: ADDR_C = 5'b0;             // CALL                           b0222
      9'b0111111??: ADDR_C = 5'b0;             // RETI, SWI, HALT, and BRANCH    b0223
      9'b011100111: ADDR_C = 5'b0;             // CLC                            b0224
      9'b011101011: ADDR_C = 5'b0;             // SRIS                           b0225
      default:      ADDR_C = IDU_IREG[23:19];  // else                           b0226
    endcase                                                                      b0227
                                                                                 b0228
  end                                                                            b0229
                                                                                 b0230
  //--------------------------------------------------------------------------   b0231
  //                                                                             b0232
  // Decode group DG3                                                            b0233
  //                                                                             b0234
  // With changing instruction register,                                         b0235
  // enable register, or exception,                                              b0236
  // update all relevant outputs                                                 b0237
  //                                                                             b0238
  //--------------------------------------------------------------------------   b0239
                                                                                 b0240
  always @(IDU_IREG or IDU_DEREG or EXCEPT_RQ) begin : DG3                       b0241
                                                                                 b0242
    //                                                                           b0243
    // Update SREG_ACC_DIR depending on instruction,                             b0244
    // enable state, and exception request                                       b0245
    //                                                                           b0246
    casez({EXCEPT_RQ, IDU_DEREG, IDU_IREG[31:24]})                               b0247
      10'b0111101011: SREG_ACC_DIR = 1'b1;       // valid SRIS instruction       b0248
      default:        SREG_ACC_DIR = 1'b0;       // other instructions           b0249
    endcase                                                                      b0250
                                                                                 b0251
    //                                                                           b0252
    // Update SWI_RQ depending on instruction,                                   b0253
    // enable state, and exception request                                       b0254
    //                                                                           b0255
    case({EXCEPT_RQ, IDU_DEREG, IDU_IREG[31:24]})                                b0256
      10'b0111111101: SWI_RQ = 1'b1;   // valid SWI instruction                  b0257
      default:        SWI_RQ = 1'b0;   // other instructions                     b0258
    endcase                                                                      b0259
                                                                                 b0260
    //                                                                           b0261
    // Update NEW_FLAGS depending on instruction class,                          b0262
    // enable state, and exception request                                       b0263
    //                                                                           b0264
    case({EXCEPT_RQ, IDU_DEREG, IDU_IREG[31:30]})                                b0265
      4'b0101: NEW_FLAGS = IDU_IREG[25];   // valid ALU instruction              b0266
      default: NEW_FLAGS = 1'b0;           // other instructions                 b0267
    endcase                                                                      b0268
                                                                                 b0269
  end                                                                            b0270
                                                                                 b0271