3_03idu

大型risc处理器设计源代码,这是书中的代码 基于流水线的risc cpu设计

//----------------------------------------------------------------------------   b0000
//                                                                               b0001
// IDU: module of instruction decode unit                                        b0002
//                                                                               b0003
// This module determines the control signals necessary                          b0004
// for execution of the present instruction. It observes the                     b0005
// present processor kernel/user mode and exception requests.                    b0006
//                                                                               b0007
// The following exception requests are generated by the IDU:                    b0008
// 'Unimplemented Instruction':  pseudo-instructions MUL and DIV                 b0009
// 'Illegal Instruction':        undefined instruction code                      b0010
// 'Privilege Violation':        KERNEL instruction in USER mode                 b0011
//                                                                               b0012
// KERNEL instructions are:                                                      b0013
// HALT, RETI, and CLC,                                                          b0014
// LRFS reading special registers different from PC, RPC, LPC, and SR,           b0015
// SRIS writing special registers different from PC, RPC, LPC, and SR            b0016
//                                                                               b0017
// A delayed CTR exception requested by the IFU is                               b0018
// forwarded by the IDU with an appropriate exception code.                      b0019
// This exception occurs if the IFU detects a BRANCH,                            b0020
// CALL, SWI, or SRIS PC as a delay instruction                                  b0021
// of BRANCH, CALL, SWI, or SRIS PC.                                             b0022
//                                                                               b0023
//----------------------------------------------------------------------------   b0024
                                                                                 b0025
module idu (                                                                     b0026
    IMMEDIATE, SWI_ID, EXCEPT_ID,                                                b0027
    ADDR_A, ADDR_B, ADDR_C, ADDR_D, ADDR_SREG,                                   b0028
    ALU_OPCODE, MAU_ACC_MODE2, MAU_OPCODE2,                                      b0029
    USE_SREG_DATA, USE_IMMEDIATE, SWI_RQ, EXCEPT_RQ,                             b0030
    SREG_ACC_DIR, DO_RETI, DO_HALT, NEW_FLAGS, CCLR,                             b0031
    I_BUS,                                                                       b0032
  CP, WORK_ID, STEP, KILL_IDU, nRESET, ID_KUMODE, EXCEPT_CTR                     b0033
  );                                                                             b0034
                                                                                 b0035
  // Outputs                                                                     b0036
  output [31:0] IMMEDIATE;       // IMMEDIATE operand B                          b0037
  output [ 3:0] SWI_ID;          // software interrupt code                      b0038
  output [ 2:0] EXCEPT_ID;       // exception interrupt code                     b0039
  output [ 4:0] ADDR_A,          // address of register operand A                b0040
                ADDR_B,          // address of register operand B                b0041
                ADDR_C,          // address of destination register C            b0042
                ADDR_D;          // register address of write data               b0043
  output [ 3:0] ADDR_SREG;       // address of special register                  b0044
  output [ 3:0] ALU_OPCODE;      // ALU opcode                                   b0045
  output [ 2:0] MAU_ACC_MODE2,   // MAU access mode                              b0046
                MAU_OPCODE2;     // MAU opcode                                   b0047
  output        USE_SREG_DATA,   // B operand is SREG                            b0048
                USE_IMMEDIATE,   // B operand is IMMEDIATE                       b0049
                SWI_RQ,          // SWI request                                  b0050
                EXCEPT_RQ,       // exception request                            b0051
                SREG_ACC_DIR,    // access direction to SREG                     b0052
                DO_RETI,         // RETI request                                 b0053
                DO_HALT,         // HALT request                                 b0054
                NEW_FLAGS,       // flags changing                               b0055
                CCLR;            // request of clear cache                       b0056
                                                                                 b0057
  // Inputs                                                                      b0058
  input  [31:0] I_BUS;           // instruction bus                              b0059
  input         CP,              // system clock                                 b0060
                WORK_ID,         // work enable                                  b0061
                STEP,            // pipeline enable                              b0062
                KILL_IDU,        // disable decoding                             b0063
                nRESET,          // reset                                        b0064
                ID_KUMODE,       // processor mode                               b0065
                EXCEPT_CTR;      // CTR exception request                        b0066
                                                                                 b0067
  reg    [31:0] IMMEDIATE;       // IMMEDIATE operand B                          b0068
  reg    [ 3:0] SWI_ID;          // software interrupt code                      b0069
  reg    [ 2:0] EXCEPT_ID;       // exception interrupt code                     b0070
  reg    [ 4:0] ADDR_A,          // address of register operand A                b0071
                ADDR_B,          // address of register operand B                b0072
                ADDR_C,          // address of destination register C            b0073
                ADDR_D;          // register address of write data               b0074
  reg    [ 3:0] ADDR_SREG;       // address of special register                  b0075
  reg    [ 3:0] ALU_OPCODE;      // ALU opcode                                   b0076
  reg    [ 2:0] MAU_ACC_MODE2,   // MAU access mode                              b0077
                MAU_OPCODE2;     // MAU opcode                                   b0078
  reg           USE_SREG_DATA,   // B operand is SREG                            b0079
                USE_IMMEDIATE,   // B operand is IMMEDIATE                       b0080
                SWI_RQ,          // SWI request                                  b0081
                EXCEPT_RQ,       // exception request                            b0082
                SREG_ACC_DIR,    // access direction to SREG                     b0083
                DO_RETI,         // RETI request                                 b0084
                DO_HALT,         // HALT request                                 b0085
                NEW_FLAGS,       // flags changing                               b0086
                CCLR;            // request of clear cache                       b0087
                                                                                 b0088
  wire   [31:0] I_BUS;           // instruction bus                              b0089
  wire          CP,              // system clock                                 b0090
                WORK_ID,         // work enable                                  b0091
                STEP,            // pipeline enable                              b0092
                KILL_IDU,        // disable decoding                             b0093
                nRESET,          // reset                                        b0094
                ID_KUMODE,       // processor mode                               b0095
                EXCEPT_CTR;      // CTR exception request                        b0096
                                                                                 b0097
  reg    [31:0] IDU_IREG;        // instruction register                         b0098
  reg           IDU_DEREG;       // IDU decode enable register                   b0099
                                                                                 b0100
  //                                                                             b0101
  // When RESET, initialize instruction register                                 b0102
  // with instruction NOP (XOR R00,R00,R00)                                      b0103
  //                                                                             b0104
  always @(nRESET) begin                                                         b0105
    while (~nRESET) begin                                                        b0106
      IDU_IREG = 32'h49000000;                                                   b0107
      IDU_DEREG = 1'b1;                                                          b0108
      #1;                                                                        b0109
    end                                                                          b0110
  end                                                                            b0111
                                                                                 b0112
  //                                                                             b0113
  // Load instruction register                                                   b0114
  //                                                                             b0115
  //                                                                             b0116
  always @(posedge CP) if (WORK_ID) IDU_IREG = #`DELTA I_BUS;                    b0117
                                                                                 b0118
  //                                                                             b0119
  // Load decode enable register                                                 b0120
  //                                                                             b0121
  //                                                                             b0122
  always @(posedge CP) if (STEP) IDU_DEREG = #`DELTA ~KILL_IDU;                  b0123
                                                                                 b0124
  //--------------------------------------------------------------------------   b0125
  //                                                                             b0126
  // Decode group DG1                                                            b0127
  //                                                                             b0128
  // Update all outputs depending                                                b0129
  // on instruction register                                                     b0130
  //                                                                             b0131
  //--------------------------------------------------------------------------   b0132
                                                                                 b0133
  always @(IDU_IREG) begin : DG1                                                 b0134
                                                                                 b0135